ADV7174BCP datasheet(44/52 Pages) AD

44 / 52 page

ADV7174/ADV7179

Rev. A | Page 44 of 52

APPENDIX 5—TELETEXT

TELETEXT INSERTION

tPD is the time needed by the ADV7174/ADV7179 to interpolate

input data on TTX and insert it onto the CVBS or Y outputs,

such that it appears tSYNTTXOUT = 10.2 µs after the leading edge of

the horizontal signal. Time TTXDEL is the pipeline delay time by

the source that is gated by the TTXREQ signal in order to

deliver TTX data.

With the programmability offered with the TTXREQ signal on

the rising/falling edges, the TTX data is always inserted at the

correct position of 10.2 µs after the leading edge of horizontal

sync pulse, thus enabling a source interface with variable pipe-

line delays.

The width of the TTXREQ signal must always be maintained to

allow the insertion of 360 (to comply with the Teletext standard

PAL-WST) Teletext bits at a text data rate of 6.9375 Mbits/s.

This is achieved by setting TC03–TC00 to 0. The insertion

window is not open if the Teletext enable bit (MR35) is set to 0.

TELETEXT PROTOCOL

The relationship between the TTX bit clock (6.9375 MHz) and

the system clock (27 MHz) for 50 Hz is

() 027777

9375

⎟

⎠

⎞

⎜

⎝

⎛

MHz

Thus, 37 TTX bits correspond to 144 clocks (27 MHz) and each

bit has a width of almost four clock cycles. The ADV7174/

ADV7179 uses an internal sequencer and variable phase inter-

polation filter to minimize the phase jitter and thus generate a

band-limited signal that can be output on the CVBS and Y

outputs.

At the TTX input, the bit duration scheme repeats after every 37

TTX bits or 144 clock cycles. The protocol requires that TTX

Bits 10, 19, 28, and 37 are carried by three clock cycles and all

other bits by four clock cycles. After 37 TTX bits, the next bits

with three clock cycles are 47, 56, 65, and 74. This scheme holds

for all following cycles of 37 TTX bits until all 360 TTX bits are

completed. All Teletext lines are implemented in the same way.

Individual control of Teletext lines is controlled by Teletext

setup registers.

ADDRESS AND DATA

RUN-IN CLOCK

TELETEXT VBI LINE

45 BYTES (360 BITS) – PAL

Figure 59. Teletext VBI Line

PROGRAMMABLE PULSE EDGES

tPD

CVBS/Y

HSYNC

TTXREQ

TTXDATA

tSYNTTXOUT = 10.2µs

tPD = PIPELINE DELAY THROUGH ADV7174/ADV7179

TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])

tSYNTTXOUT

10.2

µs

TTXDEL

TTXST

Figure 60. Teletext Functionality

ADV7174BCP Datasheet(PDF) 44 Page - Analog Devices

ADV7174BCP Datasheet(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL