ADV7174BCP datasheet(28/52 Pages) AD

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ADV7174/ADV7179

Rev. A | Page 28 of 52

MODE REGISTER 0 (MR0)

Bits:

MR07 – MR00

Address:

SR4–SR0 = 00H

Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to.

CHROMA FILTER SELECT

MR07 MR06

1.3 MHz LOW-PASS FILTER

MR05

0.65 MHz LOW-PASS FILTER

1.0 MHz LOW-PASS FILTER

2.0 MHz LOW-PASS FILTER

RESERVED

CIF

QCIF

RESERVED

MR01

MR00

MR07

MR02

MR03

MR05

MR06

MR04

OUTPUT VIDEO

STANDARD SELECTION

MR01 MR00

NTSC

PAL (B, D, G, H, and I)

PAL (M)

RESERVED

LUMA FILTER SELECT

MR04 MR03

LOW-PASS FILTER (NTSC)

MR02

LOW-PASS FILTER (PAL)

NOTCH FILTER (NTSC)

NOTCH FILTER (PAL)

EXTENDED MODE

CIF

QCIF

RESERVED

Figure 38. Mode Register 0

Table 9. MR0 Bit Description

Bit Name

Bit No.

Description

Output Video Standard

Selection

MR01–MR00

These bits are used to set up the ENCODE mode. The ADV7174/ADV7179 can be set up to

output NTSC, PAL (B/D/G/H/I), and PAL (M and N) standard video.

PAL M is available on the ADV7174 only.

Luminance Filter Control

MR02–MR04

These bits specify which luminance filter is to be selected. The filter selection is made

independent of whether PAL or NTSC is selected.

Chrominance Filter Control

MR05–MR07

These bits select the chrominance filter. A low-pass filter can be selected with a choice of

cutoff frequencies 0.65 MHz, 1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF or QCIF

filters.

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