ADV7174BCP datasheet(32/52 Pages) AD

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ADV7174/ADV7179

Rev. A | Page 32 of 52

MODE REGISTER 4 (MR4)

Bits:

MR47–MR40

Address:

SR4–SR0 = 04H

Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4.

MR41

MR40

MR47

MR42

MR44

MR43

MR45

MR46

OUTPUT SELECT

YC OUTPUT

RGB/YPbPr OUTPUT

MR40

RGB SYNC

DISABLE

ENABLE

MR42

PEDESTAL

CONTROL

PEDESTAL OFF

PEDESTAL ON

MR44

SLEEP MODE

CONTROL

DISABLE

ENABLE

MR46

ACTIVE VIDEO

FILTER CONTROL

DISABLE

ENABLE

MR45

MR47

(0)

ZERO SHOULD

BE WRITTEN TO

THIS BIT

VSYNC_3H

DISABLE

ENABLE

MR43

RGB/YUV

CONTROL

RGB OUTPUT

YPbPr OUTPUT

MR41

Figure 42. Mode Register 4

Table 14. MR4 Bit Description

Bit Name

Bit No.

Description

Output Select

MR40

This bit specifies if the part is in composite video or RGB/YPbPr mode.

RGB/YPbPr Control

MR41

This bit enables the output from the RGB DACs to be set to YPbPr output video standard.

RGB Sync

MR42

This bit is used to set up the RGB outputs with the sync information encoded on all RGB

outputs.

VSYNC_3H

MR43

When this bit is enabled (1) in slave mode, it is possible to drive the VSYNC active low

input for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in

master mode, the ADV7174/ADV7179 outputs an active low VSYNC signal for three lines

in NTSC mode and 2.5 lines in PAL mode.

Pedestal Control

MR44

This bit specifies whether a pedestal is to be generated on the NTSC composite video

signal. This bit is invalid if the ADV7174/ ADV7179 is configured in PAL mode.

Active Video Filter Control

MR45

This bit controls the filter mode applied outside the active video portion of the line. This

filter ensures that the sync rise and fall times are always on spec regardless of which luma

filter is selected. A Logic 1 enables this mode.

Sleep Mode Control

MR46

When this bit is set (1), sleep mode is enabled. With this mode enabled, the

ADV7174/ADV7179 power consumption is reduced to typically 200 nA. The I2C registers

can be written to and read from when the ADV7174/ADV7179 is in sleep mode. If MR46 is

set to a (0) when the device is in sleep mode, the ADV7174/ADV7179 comes out of sleep

mode and resumes normal operation. Also, if the RESET signal is applied during sleep

mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation.

Reserved

MR47

A Logic 0 should be written to this bit.

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