ADV7174/ADV7179

Rev. A | Page 34 of 52

TIMING MODE REGISTER 1 (TR1)

Bits:

TR17–TR10

Address:

SR4–SR0 = 08H

Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register

can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.

TR11

TR10

TR17

TR12

TR13

TR15

TR16

TR14

HSYNC TO PIXEL

DATA ADJUST

TR17 TR16

00

× T

PCLK

1

× T

PCLK

1

× T

PCLK

4

× T

PCLK

16

× T

PCLK

128

× T

PCLK

0

× T

PCLK

4

× T

PCLK

8

× T

PCLK

16

× T

PCLK

1

× T

PCLK

4

× T

PCLK

16

× T

PCLK

128

× T

PCLK

2

× T

PCLK

3

× T

PCLK

0

1

1

0

1

0

1

HSYNC TO

FIELD/VSYNC DELAY

TR13 TR12

0

0

1

1

0

1

0

1

HSYNC WIDTH

0

0

1

1

0

1

0

1

TR11 TR10

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

x

0

1

TR15 TR14

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

0

0

1

1

0

1

0

1

LINE 313

LINE 314

LINE 1

TIMING MODE 1 (MASTER/PAL)

HSYNC

FIELD/VSYNC

Figure 44. Timing Register 1

Table 16. TR1 Bit Description

Bit Name

Bit No.

Description

HSYNC Width

TR11–TR10

These bits adjust the HSYNC pulse width.

HSYNC to FIELD/VSYNC

Delay

TR13–TR12

These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output.

HSYNC to FIELD Rising

Edge Delay

TR15–TR14

When the ADV7174/ADV7179 is in Timing Mode 1, these bits adjust the position of the HSYNC

output relative to the FIELD output rising edge.

VSYNC Width

TR15–TR14

When the ADV7174/ADV7179 is configured in Timing Mode 2, these bits adjust the VSYNC

pulse width.

HSYNC to Pixel Data Adjust

TR17–TR16

This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb

components to be swapped. This adjustment is available in both master and slave timing modes.