ADV7174BCP datasheet(16/52 Pages) AD

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ADV7174/ADV7179

Rev. A | Page 16 of 52

FEATURES

COLOR BAR GENERATION

The ADV7174/ADV7179 can be configured to generate 100/

7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color

bars. These are enabled by setting MR17 of Mode Register 1 to

Logic 1.

SQUARE PIXEL MODE

The ADV7174/ADV7179 can be used to operate in square pixel

mode. For NTSC operation, an input clock of 24.5454 MHz is

required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal timing logic adjusts accord-

ingly for square pixel mode operation.

COLOR SIGNAL CONTROL

The color information can be switched on and off the video

output using Bit MR24 of Mode Register 2.

BURST SIGNAL CONTROL

The burst information can be switched on and off the video

output using Bit MR25 of Mode Register 2.

NTSC PEDESTAL CONTROL

The pedestal on both odd and even fields can be controlled on a

line-by-line basis using the NTSC pedestal control registers.

This allows the pedestals to be controlled during the vertical

blanking interval.

PIXEL TIMING DESCRIPTION

The ADV7174/ADV7179 operates in an 8-bit YCrCb mode.

8-Bit YCrCb Mode

This default mode accepts multiplexed YCrCb inputs through

the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0

Cr0, Y1, Cb1, Y2, and so on. The Y, Cb, and Cr data are input on

a rising clock edge.

SUBCARRIER RESET

Together with the SCRESET/RTC pin and Bits MR22 and

MR21 of Mode Register 2, the ADV7174/ADV7179 can be used

in subcarrier reset mode. The subcarrier resets to Field 0 at the

start of the following field when a low-to-high transition occurs

on this input pin.

REAL-TIME CONTROL

Together with the SCRESET/RTC pin and Bits MR22 and MR21

of Mode Register 2, the ADV7174/ADV7179 can be used to

lock to an external video source. The real-time control mode

allows the ADV7174/ADV7179 to automatically alter the

subcarrier frequency to compensate for line length variation.

When the part is connected to a device that outputs a digital

data stream in the RTC format (such as a ADV7183A video

decoder; see Figure 19), the part automatically changes to the

compensated subcarrier frequency on a line-by-line basis. This

digital data stream is 67 bits wide and the subcarrier is contained

in Bits 0 to 21. Each bit is two clock cycles long. 00H should be

written into all four subcarrier frequency registers when using

this mode.

Video Timing Description

The ADV7174/ADV7179 is intended to interface with off-the-

shelf MPEG1 and MPEG2 decoders. Consequently, the

ADV7174/ADV7179 accepts 4:2:2 YCrCb pixel data via a

CCIR-656 pixel port and has several video timing modes of

operation that allow it to be configured as either a system

master video timing generator or as a slave to the system video

timing generator. The ADV7174/ADV7179 generates all of the

required horizontal and vertical timing periods and levels for

the analog video outputs.

The ADV7174/ADV7179 calculates the width and placement of

analog sync pulses, blanking levels, and color burst envelopes.

Color bursts are disabled on appropriate lines, and serration and

equalization pulses are inserted where required.

In addition, the ADV7174/ADV7179 supports a PAL or NTSC

square pixel operation in slave mode. The part requires an input

pixel clock of 24.5454 MHz for NTSC and an input pixel clock

of 29.5 MHz for PAL. The internal horizontal line counters

place the various video waveform sections into the correct

location for the new clock frequencies.

The ADV7174/ADV7179 has four distinct master and four

distinct slave timing configurations. Timing control is

established with the bidirectional HSYNC, BLANK, and

FIELD/VSYNC pins. Timing Mode Register 1 can also be used

to vary the timing pulse widths and where they occur in

relation to each other.

ADV7174BCP Datasheet(PDF) 16 Page - Analog Devices

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