AD7617 datasheet(13/52 Pages) AD

13 / 52 page

AD7617

Data Sheet

Rev. 0 | Page 12 of 51

Pin No.

Type1

Mnemonic2

Description

AI GND

V3AGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3A.

V3A

Analog Input for Channel 3, ADC A.

AI GND

V2AGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2A.

V2A

Analog Input for Channel 2, ADC A.

AI GND

V1AGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1A.

V1A

Analog Input for Channel 1, ADC A.

AI GND

V0AGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0A.

V0A

Analog Input for Channel 0, ADC A.

CAP

REFCAP

Reference Buffer Output Force/Sense Pin. Decouple this pin to REFGND using a low effective

series resistance (ESR), 10 µF, X5R ceramic capacitor, as close to the REFCAP pin as possible.

The voltage on this pin is typically 4.096 V.

CAP

REFGND

Reference Ground Pin. Connect this pin to AGND.

REF

REFINOUT

Reference Input/Reference Output. The on-chip reference of 2.5 V is available on this pin for

external use when the REFSEL pin is set to logic high. Alternatively, the internal reference can

be disabled by setting the REFSEL pin to logic low, and an external reference of 2.5 V can be

applied to this input. Decoupling is required on this pin for both the internal and external

reference options. Connect a 100 nF, X7R capacitor between the REFINOUT and REFINOUTGND

pins, as close to the REFINOUT pin as possible. If using an external reference, connect a 10 kΩ

series resistor to this pin to band limit the reference signal.

CAP

REFINOUTGND

Reference Input, Reference Output Ground Pin.

REFSEL

Internal/External Reference Selection Input. REFSEL is a logic input. If this pin is set to logic

high, the internal reference is selected and enabled. If this pin is set to logic low, the internal

reference is disabled, and an external reference voltage must be applied to the REFINOUT pin.

The signal state is latched on the release of a full reset and requires an additional full reset to

reconfigure.

RESET

Reset Input. Connect a 100 pF capacitor between RESET and ground. Full and partial reset

options are available. The type of reset is determined by the length of the RESET pulse.

Keeping RESET low places the device into shutdown mode. See the Reset Functionality

section for further details.

SEQEN

Channel Sequencer Enable Input (Hardware Mode Only). When SEQEN is tied low, the

sequencer is disabled.

When SEQEN is high, the sequencer is enabled (with restricted functionality in hardware

mode). See the Sequencer section for further details. The signal state is latched on the release

of a full reset, and requires an additional full reset to reconfigure.

In software mode, this pin must be connected to DGND.

38, 39

HW_RNGSEL1,

HW_RNGSEL0

Hardware/Software Mode Selection, Hardware Mode Range Select Inputs. Hardware/software

mode selection is latched at full reset. Range selection in hardware mode is not latched.

HW_RNGSELx = 00: software mode; the AD7617 is configured via the software registers.

HW_RNGSELx = 01: hardware mode; analog input range is ±2.5 V.

HW_RNGSELx = 10: hardware mode; analog input range is ±5 V.

HW_RNGSELx = 11: hardware mode; analog input range is ±10 V.

SER/PAR

Serial/Parallel Interface Selection Input. Logic input. If this pin is tied to logic low, the parallel

interface is selected. If this pin is tied to logic high, the serial interface is selected. The signal

state is latched on the release of a full reset, and requires an additional full reset to reconfigure.

41, 42, 43,

DO/DI

DB0, DB1, DB2,

DB3

Parallel Output/Input Data Bit 0 to Data Bit 3. In parallel mode, DB2 is the LSB of the 14-bit

conversion result and DB0 and DB1output zero. In software parallel mode, DB0, DB1, DB2, and

DB3 are the four LSBs of a register write/read operation. In hardware parallel mode, DB0 and

DB1 can be left floating or pulled to DGND via a 10 kΩ pull-down resistor. Refer to the Parallel

Interface section for further details. In serial mode, these pins must be tied to DGND.

AD7617 Datasheet(PDF) 13 Page - Analog Devices

AD7617 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL