AD7617

Data Sheet

Rev. 0 | Page 14 of 51

Pin No.

Description

62

DI

SCLK/RD

Serial Clock Input/Parallel Data Read Control Input. In serial mode, this pin acts as the serial

clock input for data transfers. The CS falling edge takes the SDOA and SDOB data output lines

out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK

clocks all subsequent data bits onto the SDOA and SDOB serial data outputs.

When both CS and RD are logic low in parallel mode, the output bus is enabled.

63

DI

CS

Chip Select. This active low logic input frames the data transfer.

In parallel mode, when both CS and RD are logic low, the DBx output bus is enabled, and the

conversion result is output on the parallel data bus lines.

In serial mode, CS frames the serial read transfer and clocks out the MSB of the serial output data.

64, 65, 66

DI

CHSEL0, CHSEL1,

CHSEL2

Channel Selection Input 0 to Input 2. In hardware mode, these inputs select the input

channels for the next conversion in Channel Group A and Channel Group B. For example,

CHSELx = 0x000 selects V0A and V0B for the next conversion; CHSELx = 0x001 selects V1A and

V1B for the next conversion.

In software mode, these pins must be connected to DGND.

67

DO

BUSY

Busy Output. This pin transitions to a logic high after a CONVST rising edge and indicates that

the conversion process started. The BUSY output remains high until the conversion process

for the current selected channels completes. The falling edge of BUSY signals that the

conversion data is being latched into the output data registers and is available to read. Data

must be read after BUSY returns to low. Rising edges on CONVST have no effect while the

BUSY signal is high.

68

DI

CONVST

Conversion Start Input for Channel Group A and Channel Group B. This logic input initiates

conversions on the analog input channels.

A conversion initiates when CONVST transitions from low to high for the selected analog

input pair. When burst mode and oversampling mode are disabled, every CONVST transition

from low to high converts one channel pair. In sequencer mode, when burst mode or

oversampling is enabled, a single CONVST transition from low to high is necessary to perform

the required number of conversions.

69

CAP

REGGND

Internal Analog Regulator Ground. This pin must connect to the AGND plane of a system.

70

CAP

REGCAP

Decoupling Capacitor Pin for Voltage Output from Internal Analog Regulator. Decouple this

output pin separately to REGGND using a 10 μF capacitor. The voltage at this pin is 1.87 V

typical.

73

AI

V0B

Analog Input for Channel 0, ADC B.

74

AI GND

V0BGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V0B.

75

AI

V1B

Analog Input for Channel 1, ADC B.

76

AI GND

V1BGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V1B.

77

AI

V2B

Analog Input for Channel 2, ADC B.

78

AI GND

V2BGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V2B.

79

AI

V3B

Analog Input for Channel 3, ADC B.

80

AI GND

V3BGND

Analog Input Ground Pin. This pin corresponds to Analog Input Pin V3B.

1

AI is analog input, GND is ground, P is power supply, CAP is decoupling capacitor pin, REF is reference input/output, DI is digital input, and DO is digital output.

2

Note that throughout this data sheet, multifunction pins, such as SER/PAR, are referred to either by the entire pin name or by a single function of the pin, for example,

SER, when only that function is relevant.