Electronic Components Datasheet Search
  English  ▼

X  

AD9633 Datasheet(PDF) 35 Page - Analog Devices

Part # AD9633
Description  125 MSPS, Serial LVDS 1.8 V ADC
PDF  42 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9633 Datasheet(HTML) 35 Page - Analog Devices

Back Button AD9633 Datasheet HTML 31Page - Analog Devices AD9633 Datasheet HTML 32Page - Analog Devices AD9633 Datasheet HTML 33Page - Analog Devices AD9633 Datasheet HTML 34Page - Analog Devices AD9633 Datasheet HTML 35Page - Analog Devices AD9633 Datasheet HTML 36Page - Analog Devices AD9633 Datasheet HTML 37Page - Analog Devices AD9633 Datasheet HTML 38Page - Analog Devices AD9633 Datasheet HTML 39Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 35 / 42 page
background image
AD9633
Data Sheet
Rev. B | Page 34 of 41
MEMORY MAP REGISTER TABLE
The AD9633 uses a 3-wire interface and 16-bit addressing and,
therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3
and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high,
the SPI enters a soft reset, where all of the user registers revert
to their default values and Bit 2 is automatically cleared.
Table 17.
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0 =
SDO
active
LSB first
Soft reset
1 =
16-bit
address
1 =
16-bit
address
Soft
reset
LSB first
0 = SDO
active
0x18
The nibbles
are mirrored
so that LSB-
first or MSB-
first mode
registers
correctly.
The default
for ADCs is
16-bit mode.
0x01
Chip ID (global)
8-bit chip ID, Bits[7:0]
AD9633 0x90 = quad 12-bit 80 MSPS/105 MSPS/125 MSPS serial LVDS
0x90
Unique
chip ID
used to differ-
entiate
devices; read
only.
0x02
Chip grade
(global)
Open
Speed grade ID[6:4]
100 = 80 MSPS
101 = 105 MSPS
110 = 125 MSPS
Open
Open
Open
Open
Unique speed
grade ID used
to differentiate
graded devices;
read only.
Device Index and Transfer Registers
0x05
Device index
Open
Open
Clock
Channel
DCO
Clock
Channel
FCO
Data
Channel
D
Data
Channel
C
Data
Channel
B
Data
Channel
A
0x3F
Bits are set
to determine
which device
on chip receives
the next write
command. The
default is all
devices on chip.
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Initiate
override
0x00
Set resolution/
sample rate
override.
Global ADC Function Registers
0x08
Power modes
(global)
Open
Open
External
power-
down pin
function
0 = full
power-
down
1 =
standby
Open
Open
Open
Power mode
00 = chip run
01 = full power-down
10 = standby
11 = reset
0x00
Determines
various generic
modes of chip
operation.
0x09
Clock (global)
Open
Open
Open
Open
Open
Open
Open
Duty
cycle
stabilize
0 = off
1 = on
0x01
Turns duty cycle
stabilizer on or
off.
0x0B
Clock divide
(global)
Open
Open
Open
Open
Open
Clock divide ratio[2:0]
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com