AD9633 datasheet(38/42 Pages) AD

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Data Sheet

AD9633

Rev. B | Page 37 of 41

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Interfacing to High Speed ADCs via SPI.

Device Index (Register 0x05)

There are certain features in the map that can be set

independently for each channel, whereas other features apply

globally to all channels (depending on context) regardless of

which are selected. The first four bits in Register 0x05 can be

used to select which individual data channels are affected. The

output clock channels can be selected in Register 0x05 as well. A

smaller subset of the independent feature list can be applied to

those devices.

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment

they are written. Setting Bit 0 of this transfer register high

initializes the settings in the ADC sample rate override register

(Address 0x100).

Power Modes (Register 0x08)

Bits[7:6]—Open

Bit 5—External Power-Down Pin Function

If set, the external PDWN pin initiates power-down mode.

If cleared, the external PDWN pin initiates standby mode.

Bits[4:2]—Open

Bits[1:0]—Power Mode

In normal operation (Bits[1:0] = 00), all ADC channels are

active.

In power-down mode (Bits[1:0] = 01), the digital datapath clocks

are disabled while the digital datapath is reset. Outputs are

disabled.

In standby mode (Bits[1:0] = 10), the digital datapath clocks

and the outputs are disabled.

During a digital reset (Bits[1:0] = 11), all the digital datapath

clocks and the outputs (where applicable) on the chip are reset,

except the SPI port. Note that the SPI is always left under

control of the user; that is, it is never automatically disabled or

in reset (except by power-on reset).

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other

low frequency noise, such as homodyne or direct conversion

receivers, chopping in the first stage of the AD9633 is a feature

that can be enabled by setting Bit 2. In the frequency domain,

chopping translates offsets and other low frequency noise to

fCLK/2 where it can be filtered.

Bits[1:0]—Open

Output Mode (Register 0x14)

Bit 7—Open

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting this bit chooses LVDS-IEEE (reduced range) option.

The default setting is LVDS-ANSI. As described in Table 18,

when LVDS-ANSI or LVDS-IEEE reduced range link is selected,

the user can select the driver termination. The driver current

is automatically selected to give the proper output swing.

Table 18. LVDS-ANSI/LVDS-IEEE Options

Output

Mode,

Bit 6

Output

Mode

Output

Driver

Termination

Output Driver

Current

LVDS-ANSI

User

selectable

Automatically

selected to give

proper swing

LVDS-IEEE

reduced

range link

User

selectable

Automatically

selected to give

proper swing

Bits[5:3]—Open

Bit 2—Output Invert

Setting this bit inverts the output bit stream.

Bit 1—Open

Bit 0—Output Format

By default, this bit is set to send the data output in twos

complement format. Resetting this bit changes the output mode

to offset binary.

Output Adjust (Register 0x15)

Bits[7:6]—Open

Bits[5:4]—Output Driver Termination

These bits allow the user to select the internal termination

resistor.

Bits[3:1]—Open

Bit 0—Output Drive

Bit 0 of the output adjust register controls the drive strength on the

LVDS driver of the FCO and DCO outputs only. The default

values set the drive to 1× while the drive can be increased to 2× by

setting the appropriate channel bit in Register 0x05 and then

setting Bit 0. These features cannot be used with the output

driver termination select. The termination selection takes prece-

dence over the 2× driver strength on FCO and DCO when both

the output driver termination and output drive are selected.

Output Phase (Register 0x16)

Bit 7—Open

Bits[6:4]—Input Clock Phase Adjust

When the clock divider (Register 0x0B) is used, the applied

clock is at a higher frequency than the internal sampling clock.

Bits[6:4] determine at which phase of the external clock the

sampling occurs. This is applicable only when the clock divider

is used. It is prohibited to select a value for Bits[6:4] that is greater

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