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AD9637

Data Sheet

Rev. A | Page 22 of 40

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 log10













In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 55).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9637.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or other methods), it should

be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 55. Ideal SNR vs. Input Frequency and Jitter

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 56, the power dissipated by the AD9637 is

proportional to its sample rate. The digital power dissipation

does not vary significantly because it is determined primarily by

the DRVDD supply and bias current of the LVDS output drivers.

400

300

350

250

200

150

SAMPLE RATE (MSPS)

65MSPS

80MSPS

50MSPS

40MSPS

20MSPS

Figure 56. Analog Core Power vs. fSAMPLE for fIN = 9.7 MHz

The AD9637 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In this state, the ADC

typically dissipates 1 mW. During power-down, the output drivers

are placed in a high impedance state. Asserting the PDWN pin

low returns the AD9637 to its normal operating mode. Note

that PDWN is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times. When

using the SPI port interface, the user can place the ADC in

power-down mode or standby mode. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section

for more details on using these features.

AD9637 Datasheet(PDF) 23 Page - Analog Devices

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