AD9637 datasheet(33/41 Pages) AD

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AD9637

Data Sheet

Rev. A | Page 32 of 40

Reg.

Addr.

(Hex)

Parameter

Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)

Comments

0x0B

Clock divide

(global)

Open

Clock divide ratio, Bits[2:0]

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

The divide

ratio is the

value plus 1.

0x0C

Enhancement

control

Open

Chop

mode

0 = off

1 = on

Open

0x00

Enables/

disables chop

mode.

0x0D

Test mode (local

except for PN

sequence resets)

User input test mode

00 = single

01 = alternate

10 = single once

11 = alternate once

(affects user input test

mode only,

Bits[3:0] = 1000)

Reset PN

long gen

Reset

short

gen

Output test mode, Bits[3:0] (local)

0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = one/zero word toggle

1000 = user input

1001 = 1-/0-bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

0x00

When set,

the test data

is placed on

the output

pins in place

of normal

data.

0x10

Offset adjust

(local)

8-bit device offset adjustment, Bits[7:0] (local)

Offset adjust in LSBs from +127 to −128 (twos complement format)

0x00

Device offset

trim.

0x14

Output mode

Open

LVDS-ANSI/

LVDS-IEEE

option

0 = LVDS-

ANSI

1 = LVDS-

IEEE reduced

range link

(global)

see Table 18

Open

Output

invert

(local)

Open

Output

format

0 = offset

binary

1 = twos

comple-

ment

(global)

0x01

Configures

the outputs

and the

format of the

data.

0x15

Output adjust

Open

Output driver

termination, Bits[1:0]

00 = none

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

Open

Output

drive

0 = 1× drive

1 = 2× drive

0x00

Determines

LVDS or other

output

properties.

0x16

Output phase

Open

Input clock phase adjust, Bits[6:4]

(value is number of input clock

cycles of phase delay)

(see Table 19)

Output clock phase adjust, Bits[3:0]

(setting = 0000 through 1011)

(see Table 20)

0x03

On devices

that use

global clock

divide,

determines

which phase

of the divider

output is

used to

supply the

output clock.

Internal

latching is

unaffected.

0x18

VREF

Open

Internal VREF adjustment

digital scheme, Bits[2:0]

000 = 1.0 V p-p

001 = 1.14 V p-p

010 = 1.33 V p-p

011 = 1.6 V p-p

100 = 2.0 V p-p

0x04

Selects

and/or

adjusts the

VREF.

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