AD9233 datasheet(20/45 Pages) AD

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AD9233

Rev. A | Page 19 of 44

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 48. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515 family of clock

drivers offers excellent jitter performance.

100Ω

0.1µF

50Ω*

LVDS DRIVER

50Ω*

CLK

*50Ω RESISTORS ARE OPTIONAL

CLK–

CLK+

ADC

AD9233

CLOCK

INPUT

CLOCK

INPUT

AD951x

Figure 48. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

directly drive CLK+ from a CMOS gate, while bypassing the

CLK− pin to ground with a 0.1 μF capacitor. Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages up to 3.6 V, making the

selection of the drive logic voltage very flexible. When driving

CLK+ with a 1.8 V CMOS signal, it is required to bias the

CLK− pin with a 0.1 μF capacitor in parallel with a 39 kΩ

resistor (see Figure 49). The 39 kΩ resistor is not required when

driving CLK+ with a 3.3 V CMOS signal (see Figure 50).

CLOCK

INPUT

0.1µF

39kΩ

AD951x

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

*50Ω RESISTOR IS OPTIONAL

CLK–

CLK+

ADC

AD9233

VCC

1kΩ

Figure 49. Single-Ended 1.8 V CMOS Sample Clock

CLOCK

INPUT

0.1µF

VCC

AD951x

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

*50Ω RESISTOR IS OPTIONAL

CLK–

CLK+

ADC

AD9233

1kΩ

Figure 50. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic perform-

ance characteristics.

The AD9233 contains a DCS that retimes the nonsampling, or

falling edge, providing an internal clock signal with a nominal

50% duty cycle. This allows a wide range of clock input duty

cycles without affecting the performance of the AD9233. Noise

and distortion performance are nearly flat for a wide range of

duty cycles when the DCS is on, as shown in Figure 31.

Jitter in the rising edge of the input is still of paramount

concern and is not reduced by the internal stabilization circuit.

The duty cycle control loop does not function for clock rates

less than 20 MHz nominally. The loop has a time constant

associated with it that needs to be considered in applications

where the clock rate can change dynamically, which requires a

wait time of 1.5 μs to 5 μs after a dynamic clock frequency

increase (or decrease) before the DCS loop is relocked to the

input signal. During the time the loop is not locked, the DCS

loop is bypassed, and the internal device timing is dependant

on the duty cycle of the input clock signal. In such an application,

it can be appropriate to disable the duty cycle stabilizer. In all

other applications, enabling the DCS circuit is recommended to

maximize ac performance.

The DCS can be enabled or disabled by setting the SDIO/DCS

pin when operating in the external pin mode (see Table 10), or

via the SPI, as described in the Table 15.

Table 10. Mode Selection (External Pin Mode)

Voltage at Pin

SCLK/DFS

SDIO/DCS

AGND

Binary (default)

DCS disabled

AVDD

Twos complement

DCS enabled (default)

JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (FIN) due to jitter (tJ) is calculated as

SNR = −20 log (2π × FIN × tJ)

In the equation, the rms aperture jitter (tJ) represents the root-

mean-square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification. IF

undersampling applications are particularly sensitive to jitter, as

shown in Figure 51.

100

1000

INPUT FREQUENCY (MHz)

3.00ps

0.05ps

MEASURED

PERFORMANCE

0.20ps

0.5ps

1.0ps

1.50ps

2.00ps

2.50ps

Figure 51. SNR vs. Input Frequency and Jitter

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