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MSP3401G Datasheet(PDF) 98 Page - Micronas

Part # MSP3401G
Description  Multistandard Sound Processor Family with Virtual Dolby Surround
PDF  104 Pages
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Manufacturer  MICRONAS [Micronas]
Direct Link  http://www.micronas.com
Logo MICRONAS - Micronas

MSP3401G Datasheet(HTML) 98 Page - Micronas

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MSP 34x1G
PRELIMINARY DATA SHEET
98
Micronas
6.5.5. NICAM Deemphasis
A J17 Deemphasis is always applied to the NICAM
signal. It is not switchable.
6.5.6. Identification Mode for A2 Stereo Systems
To shorten the response time of the identification algo-
rithm after a program change between two FM-Stereo
capable programs, the reset of the ident-filter can be
applied.
Sequence:
1. Program change
2. Reset ident-filter
3. Set identification mode back to standard B/G or M
4. Wait approx. 500 ms
5. Read stereo detection register
Note: This register is initialized during STANDARD
SELECTION and is automatically updated when Auto-
matic Sound Select (MODUS[0]=1) is on.
6.5.7. FM DC Notch
The DC compensation filter (FM DC Notch) for FM
input can be switched off. This is used to speed up the
automatic search function (see Section 6.4.7.). In nor-
mal FM-mode, the FM DC Notch should be switched
on.
6.6. Manual/Compatibility Mode:
Description of DSP Read Registers
All readable registers are 16-bit wide. Transmissions
via I2C bus have to take place in 16-bit words. Some of
the defined 16-bit words are divided into low and high
byte, thus holding two different control entities.
These registers are not writable.
6.6.1. Stereo Detection Register
for A2 Stereo Systems
Note: It is no longer necessary to read out and evalu-
ate the A2 identification level. All evaluation is per-
formed in the MSP and indicated in the STATUS regis-
ter.
6.6.2. DC Level Register
The DC level register measures the DC component of
the incoming FM signals (FM1 and FM2). This can be
used for seek functions in satellite receivers and for IF
FM frequencies fine tuning. A too low demodulation
frequency (DCO) results in a positive DC-level and
vice versa. For further processing, the DC content of
the demodulated FM signals is suppressed. The time
constant
τ, defining the transition time of the DC Level
Register, is approximately 28 ms.
Identification Mode
00 15hex
L
Standard B/G
(German Stereo)
0000 0000
00hex
RESET
Standard M
(Korean Stereo)
0000 0001
01hex
Reset of Ident-Filter
0011 1111
3Fhex
FM DC Notch
00 17hex
L
ON
0000 0000
00hex
Reset
OFF
0011 1111
3Fhex
Stereo Detection
Register
00 18hex
H
Stereo Mode
Reading
(two’s complement)
MONO
near zero
STEREO
positive value (ideal
reception: 7Fhex)
BILINGUAL
negative value (ideal
reception: 80hex)
DC Level Readout
FM1 (MSP-Ch2)
00 1Bhex
H
+L
DC Level Readout
FM2 (MSP-Ch1)
00 1Chex
H
+L
DC Level
[8000hex ... 7FFFhex]
values are 16 bit two’s
complement



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