CS62180 datasheet(9/50 Pages) CIRRUS

9 / 50 page

D7 (MSB) specifies burst mode if set to 1. When

using burst mode, the address field of the com-

mand word must be "0000", any other value will

invalidate the command, and the CS62180B

will simply ignore it. This effectively

means that the command for a burst write is 80

(hex) and a burst read is 81 (hex).

Burst mode allows the sixteen registers to be

consecutively read or written. Writing all regis-

ters allows fast initialization at power-up or

system reset. (Note that the Receiver Status Reg-

ister, RSR, is read-only, so a write during burst

mode will have no effect.) When using burst

mode, registers are read or written in address or-

der, 0000 (RSR) to 1111 (RMR3). Burst mode

ends on the first rising edge of CS. See Table 1

for a complete list of the CS62180B

on-chip registers.

ACLKI

TCLK

RCLK

RPOS

RNEG

TPOS

TNEG

CS62180B

MODE

V+

TCLK

TPOS

TNEG

RNEG

RPOS

RCLK

SCLK

SDO

SDI

TO HOST CONTROLLER

CS61535A

CS61574A or CS61575

SPS

SCLK

SDO

SDI

1.544 MHz

CLOCK

SIGNAL

CLKE

Figure 3. Interfacing to a Crystal T1 LIU.

ADDR

(T) TRANSMIT

(R) RECEIVE

0000

RSR

Receive Status Register - A read only register which reports all active receiver

alarm conditions.

0001

RIMR

Receive Interrupt Mask Register - A mask which allows selection of individual

alarm conditions for generation of hardware interrupt.

0010

BVCR

Bipolar Violation Count Register - A bipolar violation alarm is generated after

this 8 bit counter surpasses it’s user definable limit.

0011

ECR

Error Count Register - Two separate 4 bit counters, which record OOF errors,

and frame bit or CRC errors. Like BVCR, each can be preset to a saturation

point.

0100

CCR

Common Control Register - Selects global configuration options, such as:

framing mode, zero suppression, or loopback.

T/R

0101

RCR

Receive Control Register - Selects receiver specific options, such as the resync

algorithm or insertion of digital milliwatt codes.

0110

TCR

Transmit Control Register - Selects transmitter specific options, such as alarm

generation, clear or idle channel enable, and external S-bit or CRC insertion.

0111

1000

1001

TIR1

TIR2

TIR3

Transmit Idle Registers - Each bit of the three TIR registers corresponds to an

individual DS0 channel. When set, that channel is replaced with an idle code.

1010

1011

1100

TTR1

TTR2

TTR3

Transmit Transparent Registers - Each bit corresponds to a DS0 channel. When

set, that signaling and B7 zero suppression is disabled for that channel.

1101

1110

1111

RMR1

RMR2

RMR3

Receive Mark Registers - Each bit corresponds to a DS0 channel. When set, the

channel data is replaced with an idle or digital milliwatt code.

Table 1. On-Chip Registers

CS62180B

DS225PP2

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