CS62180 datasheet(26/50 Pages) CIRRUS

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When the receiver initiates an auto resync,

RSIGFR is held low, but all other output timing

will continue in the old alignment until the new

framing is found. When the new framing align-

ment is qualified, the output timing will change

to the new alignment at the beginning of the next

superframe (or at the start of frame 13 in SLC-

® mode), and RLOS will return low one bit

period before the F-bit of the second frame.

A receiver resync has no effect on the transmit

side timing or configuration, and behavior of the

output timing and RLOS pin is the same as that

for an auto resync described above. This is in

contrast to a reset initiated via the RST pin,

which clears all internal registers on the falling

edge, including the transmit side registers, resets

the output timing while RST is low, and then in-

itiates a receiver resync on the rising edge.

The time it takes the receiver to resync depends

on resync algorithm selected via RCR.2 and

RCR.3. The remaining bits in the RCR (1, 6, and

7) determine under what conditions an automatic

resync will be initiated.

Forced Resync

RCR.0: RESYNC

RESYNC (RCR.0) can be used to force a re-

ceiver resync. Toggling RCR.0 will initiate a

resync immediately on the rising edge. It must

then be cleared and set again to initiate another

resync. Toggling RCR.0 when going into loop-

back mode will force the receiver to resync to

the new frame alignment immediately. This is

faster than waiting for the internal hardware to

recognize an out-of-frame (OOF) condition and

initiating an automatic resync.

Note: A forced resync should be issued after a

change in framing mode to insure correct syn-

chronization.

Auto Resync Conditions

RCR.1: SYNCE

RCR.6: OOF

RCR.7: ARC

SYNCE (RCR.1) can be set to a "1" to com-

pletely disable automatic resync. If RCR.1 is

clear, a resync will automatically be initiated

when the conditions specified by RCR.6 and

RCR.7 are detected.

OOF (RCR.6) specifies how many framing bits

(FT or FPS channels only) must be in error be-

fore the receiver declares an out-of-frame (OOF)

condition. A resync is always initiated (unless

disabled) when an OOF is detected. If RCR.6 is

clear, an OOF is declared if 2 out of 4 FT or FPS

bits are in error. If RCR.6 is set to a one, an

OOF is declared if 2 out of 5 framing bits are

errored. Note that the setting of RCR.6 also ef-

fects the reporting of OOF events to the Receive

Status Register (RSR) and Error Count Register

(ECR). Refer to the appropriate sections below

for details.

ARC (RCR.7) declares whether the receiver will

initiate a resync on an OOF event only, or resync

on both OOF and carrier loss (RCL). If RCR.7 is

cleared, the receiver will commence resync upon

detection of either an OOF event (as defined by

RCR.6 above), or an RCL. If RCR.7 is set, the

receiver will only resync in response to an OOF

condition.

Resync Algorithm

RCR.2: SYNCT

RCR.3: SYNCC

SYNCT (RCR.2) allows you to declare how

many bits must be qualified in the framing pat-

tern before the receiver declares synchronization.

When RCR.2 is clear, 10 consecutive FT or FPS

framing bits preceding an RMSYNC rising edge

must be qualified. Setting RCR.2 to a "1" re-

quires the CS62180B to qualify 24 consecutive

FT or FPS bits preceding an RMSYNC

CS62180B

DS225PP2

CS62180 Datasheet(PDF) 26 Page - Cirrus Logic

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