CS62180 datasheet(30/50 Pages) CIRRUS

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If CCR.6 is set to a "1", RSR.2 will go high in

response to a Change of Frame Alignment

(COFA). A COFA is reported when the last re-

ceiver resync resulted in a change of frame or

multiframe alignment. RSR.2 will go high at the

same time the timing signals are reset after a

resync. (See Receiver Synchronization, above.)

Frame Bit Error

RSR.3: FERR

FERR (RSR.3) is set whenever a framing bit is

in error.

193S Frame Bit Errors: The framing bits for the

193S is the FT channel (odd F-bits). The RFER

status pin (pin 38) signals the same FT errors,

but in addition, signals FS errors as well. When

signaling a frame bit error, RFER will go high

simultaneously with the output of the offending

F-bit on RSER, and hold for 2 bit periods.

193E Frame Bit Errors: The framing bits for the

193E mode are the FPS channel (F-bits of

frames 4, 8, 12, 16, 20, and 24). The RFER

status pin (pin 38) signals the same FPS errors,

but in addition, signals CRC errors as well.

When signaling a frame bit error, RFER will go

high simultaneously with the output of the of-

fending F-bit on RSER, and hold for 2 bit

periods. When signaling a CRC error, RFER will

transition high 1/2 bit before the new superframe

to indicate a CRC error in the previous super-

frame. It goes high on the falling edge of RCLK,

and is held for only one period, returning low on

the next falling edge of RCLK.

SLC-96

® Frame Bit Errors: The framing bits for

the SLC-96

® mode is the FT channel (odd F-

bits). The RFER status pin (pin 38) signals the

same FT errors, but in addition, signals FS errors

as well. The presence of DL bits in FS bit posi-

tions will not be reported as frame bit errors on

pin RFER, or in registers RSR.3 and ECR.0-3,

and will not contribute to determining that an

OOF condition exists. When signaling a frame

bit error, RFER will go high simultaneously with

the output of the offending F-bit on RSER, and

hold for two bit periods.

T1DM Frame Bit Errors: The framing bits for

the T1DM mode are the FT and FS bits, plus the

channel 24 sync word. The RFER status pin (pin

38) signals errors in the frame bits. RFER will

go high simultaneously with the F-bit of the

frame following the frame in which the error(s)

occured, and will remain high for two bit peri-

ods.

Receive Carrier Loss

RSR.4: RCL

Carrier loss is declared when

128

±1 consecutive zero’s are detected at

RPOS/RNEG. RCL (RSR.2) and the RCL pin

(pin 36) transition high with the output of the

128

th±1 zero bit on RSER. The RCL pin will

return low as soon as the next "1" is received at

RPOS/RNEG.

Receive Yellow Alarm

RSR.5: RYEL

RYEL (RSR.5) transitions high when a yellow

alarm is detected. The format of the alarm de-

tected is determined by the settings of either

CCR.3 or CCR.5, depending on the framing for-

mat being used. The RYEL pin (pin 21) will

return low as soon as the alarm clears, that is,

when the next expected alarm bit no longer indi-

cates an alarm.

CS62180B

DS225PP2

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