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HD74AC Datasheet(PDF) 43 Page - Hitachi Semiconductor |
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HD74AC Datasheet(HTML) 43 Page - Hitachi Semiconductor |
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43 / 52 page  Design Considerations 42 4.2 Ground Bounce Ground bounce occurs as a result of the intrinsic characteristics of the leadframes and bondwires of the packages used to house CMOS devices. As edge rates and drive capability increase in advanced logic families, the effects of these intrinsic electrical characteristics become more pronounced. Figure 16 shows a simple circuit model for a device in a leadframe driving a standard test load. The inductor L1 represents the parasitic inductance in the ground lead of the package; inductor L2 represents the parasitic inductance in the power lead of the package; inductor L3 represents the parasitic inductance in the output lead of the package; the resistor R1 represents the output impedance of the device output, and the capacitor and resistor C L and RL represent the standard test load on the output of the device. R1 L1 L2 L3 I CL RL VCC Figure 16 Ground Bounce Output Model Output Voltage Output Current Inductor Voltage |
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