HD74AC datasheet(47/52 Pages) HITACHI

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Design Considerations

It is good practice to distribute decoupling capacitors evenly through the logic, placing one capacitor for

every package.

5.2 Capacitor Types

Decoupling capacitors need to be of the high K ceramic type with low equivalent series resistance (ESR),

consisting primarily of series inductance and series resistance. Capacitors using 5ZU dielectric have

suitable properties and make a good choice for decoupling capacitors; they offer minimum cost and

effective performance.

6. TTL-Compatible CMOS Designs Require Delta I

CC Consideration

The FACT product line is composed of two types of advanced CMOS circuits: HD74AC and HD74ACT

devices. HD74ACT indicates an advanced CMOS device with TTL-type input thresholds for direct

replacement of LS and ALS circuits. As this HD74ACT series is used to replace TTL, the Delta I

CCT

specification must be considered; this spec may be confusing and misleading to the engineer unfamiliar

with CMOS.

It is important to understand the concept of Delta I

CCT and how to use it within a design. First, consider

where Delta I

CCT initiates. Most CMOS input structures are of the totem pole type with an n-channel

transistor in a series with a p-channel transistor as illustrated in figure 20.

P Channel

N Channel

VCC

Internal

Logic

Input Pad

Figure 20 CMOS Input Structure

These two transistors can be modeled as variable resistors with resistances varying according to the input

voltage. The resistance of an on transistor is approximately 50

Ω while the resistance of an off transistor is

generally greater than 5 M

Ω. When the input to this structure is at either ground or V

CC, one transistor will

be on and one will be off. The total series resistance of this pair will be the combination of the two

individual resistances, greater than 5 M

Ω. The leakage current will then be less than 1 µA. When the input

is between ground and V

CC, the resistance of the on transistor will increase while the resistance of the off

transistor will decrease. The net resistance will drop due to the much larger value of the off resistance.

The total series resistance can be as low as 600

Ω. This reduction in series resistance of the input structure

will cause a corresponding increase in I

CC as current flows through the input structure. Figure 21 depicts

typical I

CC variance with input voltage for an HD74ACT device.

HD74AC Datasheet(PDF) 47 Page - Hitachi Semiconductor

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