HD74AC datasheet(44/52 Pages) HITACHI

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Design Considerations

The three waveforms shown in figure 16 depict how ground bounce is generated. The first waveform

shows the voltage (V) across the load as it is switched from a logic high to a logic low. The output slue

rate is dependent upon the characteristics of the output transistor, the inductors L1 and L3, and C

L, the load

capacitance. The second waveform shows the current that is generated as the capacitor discharges [I = C

L •

dv/dt]. The third waveform shows the voltage that is induced across the inductance in the ground lead due

to the changing currents [Vgb = –L • (di/dt)].

There are many factors which affect the amplitude of the ground bounce. Included are:

• Number of outputs switching simultaneously: more outputs results in more ground bounce.

• Type of output load: capacitive loads generate two to three times more ground bounce than typical

system traces. Increasing the capacitive load to approximately 60 to 70 pF increases ground bounce.

Beyond 70 pF, ground bounce drops off due to the filtering effect of the load. Moving the load away

from the output reduces the ground bounce.

• Location of the output pin: outputs closer to the ground pin exhibit less ground bounce than those

further away.

• Voltage: lowering V

CC reduces ground bounce.

• Test fixtures: standard test fixtures generate 30 to 50% more ground bounce than a typical system since

they use capacitive loads which both increase the AC load and form LCR tank circuits that oscillate.

Ground bounce produces several symptoms:

• Altered device states. FACT logic does not exhibit this symptom.

• Propagation delay degraduation. FACT devices are characterized not to degrade more than 250 ps per

additional output switching

• Undershoot on active outputs. The worst-case undershoot will be approximately equal to the worst-case

quiet output noise.

• Quiet output noise. FACT logic’s worst-case quiet output noise has been measured to be approximately

500 to 1100 mV in actual system applications.

Observing either one of the following rules is sufficient to avoid running into any of the problems

associated with ground bounce:

• First, use caution when driving asynchronous TTL-level inputs from CMOS octal outputs, or

• Second, use caution when running control lines (set, reset, load, clock, chip select) which are glitch-

sensitive through the same devices that drive data or address lines.

When it is not possible to avoid the above conditions, there are simple precautions available which can

minimize ground bounce noise. These are:

• Locate these outputs as close to the ground pin as possible.

• Use the lowest V

CC possible or separate the power supplies.

• Use board design practices which reduce any additive noise sources, such as crosstalk, reflections etc.

HD74AC Datasheet(PDF) 44 Page - Hitachi Semiconductor