HD74AC datasheet(16/52 Pages) HITACHI

16 / 52 page

FACT Descriptions and Family Characteristics

Load Capacitance (pF)

VCC = 5.0V

Ta = 25

°C

Figure 14 t

fall vs. Capacitance

P-Channel MOS

+VDD

-VSS

N-Channel MOS

N-Substrate

Output

Input

N-well

N+

P+

N+

P+

P-well

Figure 15 CMOS Inverter Cross Section with Latch-up Circuit Schematic

2.3 Latch-up

A major problem with CMOS has been its sensitivity to latch-up, usually attributed to high parasitic gains

and high input impedance (figure 15). FACT logic is guaranteed not to latch-up with dynamic currents of

100 mA forced into or out of the inputs or the outputs under worst case conditions (Ta = 85˚C and V

CC =

5.5 VDC). At room temperature the parts can typically withstand dynamic currents of over 450 mA. For

most designs, latch-up will not be a problem, but the designer should be aware of its causes and how to

prevent it.

FACT devices have been specifically designed to reduce the possibility of latch -up occurring; Hitachi

accomplished this by lowering the gain of the parasitic transistors, reducing N-well and p-well resistivity to

increase external drive current required to cause a parasitic to turn on, and careful design and layout to

minimize the substrate-injected current coupling to other circuit areas.

HD74AC Datasheet(PDF) 16 Page - Hitachi Semiconductor