HD74AC datasheet(51/52 Pages) HITACHI

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Design Considerations

8. Testing Disable Times of 3-State Outputs in a Transmission Line Environment

Traditionally, the disable time of a 3-state buffer has been measured from the 50% point on the disable

input, to the 10% or 90% point on the output. On a bench test site, the output waveform is generated by a

load capacitor and a pull-up/pull-down resistor. This circuit gives an RC charge/discharge curve as shown

in figure 25.

OUTPUT

Time (ns)

1234

6789 10 11 12

Figure 25 Typical Bench 3-State Waveform

ATE test sites generally are unable to duplicate the bench test structure. ATE test loads differ because they

are usually programmable and are situated away from the actual device. A commonly used test load is a

Wheatstone bridge. Figure 26 illustraters the Wheatstone bridge test structure when used on the MCT 2000

test-system to duplicate the bench load.

DUT

Figure 26 MCT Wheatstone Bridge Test Load

The voltage source provides a pull-up/pull-down voltage while the current sources provide I

OH and IOL.

When devices with slow output slew rates are tested with the ATE load, the resultant waveforms closely

approximate the bench waveform, and a high degree of correlation can be achieved. However, when

devices with high output slew rates are tested, different results are observed that make correlating tester

results with bench results more difficult. This difference is due to the transmission line properties of the

test equipment. Most disable tests are preceded by establishing a current flow through the output structure.

Typically, these currents will be between 5 mA and 20 mA. The device is then disabled, and a comparator

detects when the output has risen to the 10% or 90% level. Consider the situation where the connection

between the device under test (DUT) and the comparator is a transmission line. Visualize the device

output as a switch; the effect is easier to see. There is current flowing through the line, and then the switch

is opened. At the device end, the reflection coefficient changes from 0 to 1. This generates a current edge

HD74AC Datasheet(PDF) 51 Page - Hitachi Semiconductor