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AD7356 Datasheet(PDF) 11 Page - Analog Devices

Part # AD7356
Description  Differential Input, Dual, Simultaneous Sampling
PDF  21 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7356 Datasheet(HTML) 11 Page - Analog Devices

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AD7356
Data Sheet
Rev. B | Page 10 of 20
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation froma straight line passing
through the endpointsof the ADC transfer function. The
endpoints of the transferfunction are zero scale (1 LSB below
the first code transition)and full scale (1 LSB above the last
code transition).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Negative Full-Scale Error
Negative full-scale error is the deviation of thefirst code
transition (00 … 000) to (00 … 001) from the ideal (that is,
−VREF + 0.5 LSB)after the midscale error hasbeen adjusted out.
Negative Full-Scale Error Match
Negative full-scale error match is the difference in negative full-
scale error between the two ADCs.
Midscale Error
Midscale error is the deviation of the midscale code transition
(011 … 111) to (100 … 000) from the ideal (that is, 0 V).
Midscale Error Match
Midscale error match is the difference in midscale error
between the two ADCs.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code
transition (111 … 110) to (111 … 111) from the ideal (that is,
VREF − 1.5 LSB)after the midscale error has been adjustedout.
Positive Full-Scale Error Match
Positive full-scale error match is the differencein positive full-
scale error between the two ADCs.
ADC-to-ADC Isolation
ADC-to-ADC isolation is a measureof the level of crosstalk
between ADC A and ADC B. It is measured byapplying a full-
scale 1 MHzsine wave signal to one of the two ADCs and
applying a full-scale signal of variable frequency to the other
ADC. The ADC-to-ADCisolationis defined as the ratio of the
power of the 1 MHzsignal on the converted ADC to the power
of the noise signal on the other ADC that appears in the FFT.
The noise frequency on the unselectedchannel varies from
100 kHz to 2.5 MHz.
Power Supply RejectionRatio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the powerof a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the input varies from 5 kHzto 25 MHz.
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Common-Mode RejectionRatio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the powerof a 100 mV p-p sine
wave applied to the common-modevoltageof VIN+ and VIN−
of frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency (f)in the ADC output.
PfS is the power at frequency (fS)in the ADC output.
Track-and-Hold AcquisitionTime
The track-and-hold amplifierreturns to trackmode at the end
of a conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifierto reach
its final value, within ±0.5 LSB, aftertheendofa conversion.
Signal-to-(Noise and Distortion) Ratio(SINAD)
SINAD is the measured ratio of signal-to-(noise and distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noiseis the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantizationlevels in the digitiza-
tion process; the morelevels, the smaller thequantization noise.
The theoretical SINAD foran ideal N-bit converter with a sine
wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit
converter, SINADis 86 dB.



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