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AD7356

Data Sheet

Rev. B | Page 16 of 20

FULL POWER-DOWN MODE

Full power-down mode is intended for use in applications where

throughput rates slower than those in partial power-down mode

are required because power-up from a full power-down takes

substantially longer than that from a partial power-down. This

mode is more suited to applications in which a series of conversions

performed at a relatively high throughput rate are followed by a

long period of inactivity and, thus, power-down. When the

AD7356 is in full power-down mode, all analog circuitry is

powered down including the on-chip reference and reference

buffers. Full power-down mode is entered in a similar way as

partial power-down mode, except that the timing sequence shown

in Figure 25 must be executed twice. The conversion process

must be interrupted in a similar fashion by bringing CS high

anywhere after the second falling edge of SCLK and before the

10th falling edge of SCLK. The device enters partial power-down

mode at this point.

To reach full power-down, the next conversion cycle must be

interrupted in the same way, as shown in Figure 27. When CS is

brought high in this window of SCLKs, the part fully powers down.

Note that it is not necessary to complete the 14 or 16 SCLKs

once CS has been brought high to enter a power-down mode.

To exit full power-down mode and power-up the AD7356, perform

a dummy conversion, similar to powering up from partial power-

down. On the falling edge of CS, the device begins to power up as

long as CS is held low until after the falling edge of the 10th SCLK.

The required power-up time must elapse before a conversion

can be initiated, as shown in Figure 28.

SCLK

SDATAA

SDATAB

INVALID DATA

VALID DATA

110

THE PART BEGINS

TO POWER UP.

tPOWER-UP1

THE PART IS FULLY POWERED UP;

SEE THE POWER-UP TIMES SECTION.

Figure 26. Exiting Partial Power-Down Mode

THREE-STATE

110

SCLK

SDATAA

SDATAB

THREE-STATE

110

INVALID DATA

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

PARTIAL POWER-DOWN MODE.

THE PART ENTERS

FULL POWER-DOWN MODE.

Figure 27. Entering Full Power-Down Mode

SCLK

SDATAA

SDATAB

INVALID DATA

VALID DATA

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY POWERED UP;

SEE THE POWER-UP TIMES SECTION.

tPOWER-UP2

Figure 28. Exiting Full Power-Down Mode

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