AD7765

Rev. A | Page 6 of 32

TIMING SPECIFICATIONS

Table 3.

Parameter

Unit

Description

500

kHz min

Applied master clock frequency

40

MHz max

250

kHz min

Internal modulator clock derived from MCLK

20

MHz max

typ

SCO high period

typ

SCO low period

1

ns typ

SCO rising edge to FSO falling edge

2

ns typ

Data access time, FSO falling edge to data active

8

ns max

MSB data access time, SDO active to SDO valid

40

ns min

Data hold time (SDO valid to SCO rising edge)

9.5

ns max

Data access time (SCO rising edge to SDO valid)

2

ns typ

SCO rising edge to FSO rising edge

max

FSO low period

12

ns min

Setup time from FSI falling edge to SCO falling edge

min

FSI low period

t121

max

FSI low period

12

ns min

SDI setup time for the first data bit

12

ns min

SDI setup time

0

ns max

SDI hold time

min

Minimum time for a valid RESET pulse

5

ns min

Minimum time between the MCLK rising edge and RESET rising edge

5

ns min

Minimum time between the RESET rising edge and MCLK rising edge

min

Minimum time for a valid SYNC pulse

5

ns min

Minimum time between the MCLK falling edge and SYNC rising edge

5

ns min

Minimum time between the SYNC rising edge and MCLK falling edge

1

This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained).