AD7765 datasheet(16/33 Pages) AD

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AD7765

Rev. A | Page 15 of 32

THEORY OF OPERATION

The AD7765 features an on-chip fully differential amplifier to

feed the Σ-Δ modulator pins, an on-chip reference buffer, and a

FIR filter block to perform the required digital filtering of the

Σ-Δ modulator output. Using this Σ-Δ conversion technique

with the added digital filtering, the analog input is converted

into an equivalent digital word.

Σ-Δ MODULATION AND DIGITAL FILTERING

The input waveform applied to the modulator is sampled, and

an equivalent digital word is output to the digital filter at a rate

equal to ICLK. By employing oversampling, the quantization

noise is spread across a wide bandwidth from 0 to fICLK. This

means that the noise energy contained in the signal band of

interest is reduced (see Figure 23). To further reduce the

quantization noise, a high order modulator is employed to

shape the noise spectrum so that most of the noise energy is

shifted out of the signal band (see Figure 24).

QUANTIZATION NOISE

fICLK/2

BAND OF INTEREST

Figure 23. Σ-Δ ADC, Quantization Noise

fICLK/2

NOISE SHAPING

BAND OF INTEREST

Figure 24. Σ-Δ ADC, Noise Shaping

fICLK/2

BAND OF INTEREST

DIGITAL FILTER CUTOFF FREQUENCY

Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency

The digital filtering that follows the modulator removes the

large out-of-band quantization noise (see Figure 25) while also

reducing the data rate from fICLK at the input of the filter to

fICLK/128 or less at the output of the filter, depending on the

decimation rate used.

The AD7765 employs three FIR filters in series. By using

different combinations of decimation ratios, data can be

obtained from the AD7765 at three data rates.

The first filter receives data from the modulator at ICLK

MHz

where it is decimated 4× to output data at (ICLK/4)

MHz. The

second filter allows a choice of decimation rates: 16× or 32×.

The third filter has a fixed decimation rate of 2×. Table 6 shows

some characteristics of the digital filtering where ICLK =

MCLK/2. The group delay of the filter is defined to be the

delay to the center of the impulse response and is equal to the

computation plus the filter delays. The delay until valid data is

available (the FILTER-SETTLE status bit is set) is approximately

twice the filter delay plus the computation delay. This is listed in

terms of MCLK periods in Table 6.

–160

–140

–120

–100

–80

–60

–40

–20

300

250

200

150

100

FREQUENCY (kHz)

PASS-BAND RIPPLE = 0.1dB

–0.1dB FREQUENCY = 125.1kHz

–3dB FREQUENCY = 128kHz

STOP BAND = 156.25kHz

Figure 26. Filter Frequency Response (156.25 kHz ODR)

Table 6. Configuration with Default Filter

ICLK

Frequency

Decimation

Rate

Data State

Computation

Delay

Filter Delay

SYNC

Pass-Band

Bandwidth

FILTER-SETTLE

Output Data Rate

(ODR)

20 MHz

128×

Fully filtered

3.1 µs

174 µs

14217 × tMCLK

62.5 kHz

156.25 kHz

20 MHz

256×

Fully filtered

4.65 µs

346.8 µs

27895 × tMCLK

31.25 kHz

78.125 kHz

12.288 MHz

128×

Fully filtered

5.05 µs

283.2 µs

14217 × tMCLK

38.4 kHz

96 kHz

12.288 MHz

256×

Fully filtered

7.57 µs

564.5 µs

27895 × tMCLK

19.2 kHz

48 kHz

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