AD7765 datasheet(23/33 Pages) AD

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AD7765

Rev. A | Page 22 of 32

POWER MODES

Low Power Mode

During power-up, the AD7765 defaults to operate in normal

power mode. There is no register write required.

The AD7765 also offers low power mode. To operate the device

in low power mode, the user sets the LPWR bit in the control

low power mode has no impact on the output data rate or

available bandwidth.

SCO (O)

CONTROL REGISTER

ADDRESS 0x0001

LOW POWER MODE

DATA 0x0004

FSI (I)

SDI (I)

32 ×

tSCO

Figure 37. Write Scheme for Low Power Mode

RESET/

The AD7765 features a

PWRDWN Mode

RESET/PWRDWN pin. Holding the

input to this pin logic low places the AD7765 in power-down

mode. All internal circuitry is reset. Apply a RESET pulse to the

AD7765 after initial power-up of the device.

The AD7765 RESET pin is polled by the rising edge of MCLK.

The AD7765 device goes into reset when an MCLK rising

senses the RESET input signal to be logic low. AD7765 comes

out of RESET on the first MCLK rising edge that senses RESET

to be logic high.

The best practice is to ensure that all transitions of RESET

occur synchronously with the falling edge of MCLK; otherwise,

adhere to the timing requirements shown in Figure 38.

RESET should be kept logic low for a minimum of 1 MCLK

period for a valid reset to occur.

In cases where multiple AD7765 devices are being synchronized

using the SYNC pulse and in the case of daisy chaining multiple

AD7765 devices, a common RESET pulse must be provided in

addition to the common

MCLK

tR MIN

1 ×

tMCLK

tR HOLD

tR SETUP

RESET

SYNC and MCLK signals.

Figure 38. RESET

DECIMATION RATE PIN

Timing Synchronous to MCLK

The decimation rate of the AD7765 is selected using the

DEC_RATE pin. Table 11 shows the voltage input settings

required for each of the three decimation rates.

Table 11. DEC_RATE Pin Settings

Decimate

DEC_RATE Pin

Maximum Output Data Rate

128×

DVDD

156.25 kHz

256×

GND

78.125 kHz

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