AD7765

Rev. A | Page 28 of 32

AD7765 REGISTERS

The AD7765 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and

differential amplifier and provides an option to power down the AD7765. There are also digital gain and overrange threshold registers.

Writing to these registers involves writing the register address followed by a 16-bit data word. The register addresses, details of individual

bits, and default values are provided in this section.

CONTROL REGISTER

Table 13. Control Register (Address 0x0001, Default Value 0x0000)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

RD

OVR

RD

GAIN

0

RD

STAT

0

SYNC

0

BYPASS

REF

0

0

0

PWR

DOWN

LPWR

REF BUF

OFF

AMP

OFF

Table 14. Bit Descriptions of the Control Register

Bit

Mnemonic

Comment

14

RD OVR1, 2

Read overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register

instead of a conversion result.

13

RD GAIN

Read gain. If this bit is set, the next read operation outputs the contents of the digital gain register.

11

RD STAT

Read status. If this bit is set, the next read operation outputs the contents of the status register.

9

SYNC

Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple

devices synchronizes all filters.

7

BYPASS REF

Bypass reference. Setting this bit bypasses the reference buffer if the buffer is off.

3

PWR DOWN

Power-down. A logic high powers the device down without resetting. Writing a 0 to this bit powers the device back up.

2

LPWR

Low power mode. Set to Logic 1 when AD7765 is in low power mode.

1

REF BUF OFF

Reference buffer off. Asserting this bit powers down the reference buffer.

0

AMP OFF

Amplifier off. Asserting this bit switches the differential amplifier off.

1

Bit 14 to Bit 11 and Bit 9 are self-clearing bits.

2

Only one of the bits can be set in any write operation because it determines the contents of the next read operation.

STATUS REGISTER

Table 15. Status Register (Read Only)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

PARTNO

1

0

0

0

FILTER-

SETTLE

0

OVR

0

1

0

REF BUF

ON

AMP

ON

LPWR

DEC 1

DEC 0

Table 16. Bit Descriptions of the Status Register

Bit

Mnemonic

Comment

15

PARTNO

Part number. This bit is set to 1 for the AD7765.

10

FILTER-

SETTLE

Filter settling bit. This bit corresponds to the FILTER-SETTLE bit in the status word output in the second 16-bit read

operation. It indicates when data is valid.

9

0

Zero. This bit is set to Logic 0.

8

OVR

Overrange. If the current analog input exceeds the current overrange threshold, this bit is set.

4

REF BUF ON

Reference buffer on. This bit is set when the reference buffer is in use.

3

AMP ON

Amplifier on. This bit is set when the input amplifier is in use.

2

LPWR

Low power mode. This bit is set when operating in low power mode.

1 to 0

DEC[1:0]

Decimation rate. These bits correspond to the decimation rate in use.