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PIC16C781 Datasheet(PDF) 57 Page - Microchip Technology

Part # PIC16C781
Description  8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP, Comparators and PSMC
PDF  186 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16C781 Datasheet(HTML) 57 Page - Microchip Technology

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 2001 Microchip Technology Inc.
Preliminary
DS41171A-page 55
PIC16C781/782
6.0
TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers:TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• External enable input (T1G pin with TMR1GE bit = 1)
• Option for Timer1 to use LP oscillator if device is
configured to use INTRC w/o CLKOUT
Timer1 Control register (T1CON) is shown in Register 6-1.
Figure 6-2 is a simplified block diagram of the Timer1
module.
6.1
Timer1 Operation
Timer1 can operate in one of three modes:
1.
16-bit timer with prescaler.
2.
16-bit synchronous counter.
3.
16-bit asynchronous counter.
In Timer mode, Timer1 is incremented on every instruc-
tion cycle. In Counter mode, Timer1 is incremented on
the rising edge of the external clock input T1CKI (RA6/
OSC2/CLKOUT/T1CKI). In addition, the Counter mode
clock can be synchronized to the microcontroller clock
or run asynchronously.
In Counter and Timer modes, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the micro-
controller is using INTRC w/o CLKOUT), Timer1 can
use the LP oscillator as a clock source.
EXAMPLE 6-1:
TIMER1 INITIALIZATION
;* This code block will configure Timer1 for
;* Polling, Ext gate of int clk (Fosc/4), &
;* 1:1 prescaler.
;*
;* Wait for TMR1 overflow code included
;*
BANKSEL
TMR1L
; Select Bank 0
CLRF
TMR1L
; Clear TMR1 LSB
CLRF
TMR1H
; Clear TMR1 MSB
MOVLW
B’01000000’
; Gate, Ps 1:1
MOVWF
T1CON
; Int clk
BSF
T1CON,TMR1ON
; Enable timer
;********************************************
;* Wait for TMR1 overflow
T1_OVFL_WAIT
BANKSEL
PIR1
; Select Bank 0
T1_WAIT
;
TBFSS
PIR1,TMR1IF
; Overflow?
GOTO
T1_WAIT
; If 0, again
BCF
PIR1,TMR1IF
; Clear flag
Note 1: In Counter mode, the counter increments
on the rising edge of the clock.



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