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PIC16C781 Datasheet(PDF) 76 Page - Microchip Technology |
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PIC16C781 Datasheet(HTML) 76 Page - Microchip Technology |
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76 / 186 page ![]() PIC16C781/782 DS41171A-page 74 Preliminary 2001 Microchip Technology Inc. FIGURE 9-2: ANALOG INPUT MODEL 9.4 ADC Configuration and Conversion Example 9-2 demonstrates an ADC conversion. The RA0/AN0 pin is configured as the analog input. The ref- erence voltage selected is the device AVDD. The ADC interrupt is enabled, and the ADC conversion clock is ADRC. Clearing the GO/DONE bit during a conversion aborts the current conversion. The ADRES register is NOT updated with the partially completed ADC conversion sample. That is, the ADRES register continues to con- tain the value of the last completed conversion (or the last value written to the ADRES register). After the ADC conversion is aborted, a 2TAD wait period is required before the next acquisition is started. After this 2TAD wait period, an acquisition is automatically started on the selected channel. EXAMPLE 9-2: ADC CONVERSION ;******************************************** ;* This code block will configure the ADC ;* for polling, AVDD as reference, RC clock ;* and RA0 input. ;* ;* Conversion start & wait for complete ;* polling code included. ;* BANKSEL ADCON1 ; Select Bank 1 CLRF ADCON1 ; AVDD as VREF BSF TRISA,0 ; Set RA0 as input BSF ANSEL,0 ; Set RA0 as analog BANKSEL ADCON0 ; Select Bank0 MOVLW B’11000001’ MOVWF ADCON0 ; RC, Ch 0, ADC on ;******************************************** ;* Start & Wait for ADC complete, assumes ;* minimum acquisition delay from ;* configuration. ADC_CNVRT BANKSEL ADCON0 ; Select Bank 0 BSF ADCON0,GO ; Start convert ADC_CN_LOOP BTFSC ADCON0,GO ; Test for end GOTO ADC_CN_LOOP ; If not, wait MOVF ADRES,W ; Get result CPIN VA RS ANx 5 pF VDD VT = 0.6V VT = 0.6V ILEAKAGE RIC ≤ 1k Sampling Switch SS RSS CHOLD = DAC capacitance VSS 6V Sampling Switch 5V 4V 3V 2V 567 8 9 10 11 ( k Ω ) VDD = 51.2 pF ± 500 nA Legend: CPIN VT ILEAKAGE RIC SS CHOLD = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) various junctions |
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