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PIC16C781 Datasheet(PDF) 17 Page - Microchip Technology |
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PIC16C781 Datasheet(HTML) 17 Page - Microchip Technology |
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17 / 186 page  2001 Microchip Technology Inc. Preliminary DS41171A-page 15 PIC16C781/782 Bank 2 100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 101h TMR0 Timer0 Module’s Register xxxx xxxx 51 102h(2) PCL Program Counter's (PC) Least Significant Byte 0000 0000 23 103h(2) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 17 104h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 23 105h — Unimplemented — — 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 0000 35 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23 10Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 19 10Ch PMDATL PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 0000 0000 48 10Dh PMADRL PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0 xxxx xxxx 48 10Eh PMDATH — — PMD13 PMD12 PMD11 PMD10 PMD9 PMD8 --00 0000 47 10Fh PMADRH — — — Reserved Reserved PMA10 PMA9 PMA8 ---x xxxx 48 110h CALCON CAL CALERR CALREF — — — — — 000- ---- 85 111h PSMCCON0 SMCCL1 SMCCL0 MINDC1 MINDC0 MAXDC1 MAXDC0 DC1 DC0 0000 0000 104 112h PSMCCON1 SMCON S1APOL S1BPOL — SCEN SMCOM PWM/PSM SMCCS 000- 0000 104 113h — Unimplemented — — 114h — Unimplemented — — 115h — Unimplemented — — 116h — Unimplemented — — 117h — Unimplemented — — 118h — Unimplemented — — 119h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 91 11Ah CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 93 11Bh CM2CON1 MC1OUT MC2OUT — — — — — C2SYNC 00-- ---0 94 11Ch OPACON OPAON CMPEN — — — — — GBWP 00-- ---0 84 11Dh — Unimplemented — — 11Eh DAC DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0000 0000 79 11Fh DACON0 DAON DAOE — — — — DARS1 DARS0 00-- --00 79 TABLE 2-1: PIC16C781/782 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on Page: Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are trans- ferred to the upper byte of the program counter. See Section 2.9 for more detail. 2: These registers can be addressed from any bank. |
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