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CS4103 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CS4103 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 24 page ![]() © 2000 National Semiconductor Corporation www.national.com General Description The National Semiconductor® Geode™ CS4103 is a three port 400 Mbit/sec IEEE 1394 Physical Layer (PHY) device. The CS4103 complies to revision 2.0 of the P1394a specifi- cation. The deviceisathreeport implementationofareus- able cell design scalable from one to sixteen ports. The CS4103 supports all of the P1394a enhancements including connection debounce, arbitrated reset, ack-accel- erated arbitration, fly-by concatenation, multi-speed packet concatenation, PHY pinging, priority arbitration, and Sus- pend/Resume operation. It also implements the standard PHY-Link interface defined in IEEE specification 1394-1995 and updated in the P1394a specification for direct connec- tion with the Geode CS4210 IEEE 1394 Open Host Con- troller Interface (OHCI) device. The interface can operate in either direct or isolated mode and supports single capacitor isolation with bus hold inputs. The CS4103 provides a complete PHY solution including all bias generation, differential line drivers and receivers, single ended comparators for speed signaling, speed sig- naling current sources, bias detect, and connect detect cir- cuitry per port. It includes data and strobe encoding/ decoding functions as well as a re-time FIFO to synchro- nize the receive data to the local clock domain. The CS4103 can receive and respond to all the PHY packet types defined in revision 2.0 of the P1394a specification. It also supports Suspend and Resume port states and con- nect detect functions. The CS4103 generates the internal clocks and the Link SCLK (System Clock) based on a 24.576 MHz external crystal or a 24.576 MHz clock input. The CS4103 operates from a single 3.3V supply and supports transfers at 98.304, 196.608, and 393.216 Mbit/sec, (usually referred to as 100, 200, and 400 Mbit/sec respectively). Features IEEE 1394 Physical Layer Device (PHY) compliant with revision 2.0 of P1394a including all enhancements Scalable design from one to sixteen ports Supports data rates of 100, 200, and 400 Mbit/sec Single 3.3V supply operation Internal PLL generates SCLK and all internal clocks from a single 24.576 MHz crystal or clock Includes Cable Power Sense comparator for cable power monitoring Compatible with the Geode CS4210 OHCI Controller and other IEEE 1394 OHCI devices Supports the isolated PHY-Link interface compliant with 1394-1995 and P1394a specifications Single capacitor bus hold isolation\ Power saving modes 80-pin TQFP (Thin Quad Flat Pack) System Block Diagram Geode™ CS4210 IEEE 1394 OHCI Controller Geode™ CS4103 P1394a Physical Layer EEPROM I2C Interface PCI Interface PHY-Link Interface PCI Bus IEEE 1394 Cable Connectors July 2000 Geode™ CS4103 IEEE P1394a Physical Layer Device National Semiconductor is a registered trademark of National Semiconductor Corporation. Geode is a trademark of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. |
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