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14

Revision 1.0

3.2

BASE REGISTER DESCRIPTIONS

Table 3-4 is a register map of the CS4103’s Base registers. Table 3-5 provides the bit formats for these registers.

Table 3-4. Base Register Bit Map

Address

01234

567

00h

Physical_ID

R

PS

01h

RHB

IBR

Gap_count

02h

Extended

RSVD

Total_ports

03h

Max_speed

RSVD

Delay

04h

Link_active

Contender

Jitter

Pwr_class

05h

Resume_int

ISBR

Loop

Pwr_fail

Timeout

Port_event

Enab_accel

Enab_multi

06h

RSVD

07h

Page_select

RSVD

Port_select

Table 3-5. Base Registers

Bit

Name

Access

Reset

Description

Address 00h

0:5

Physical_ID

R

Undef

Physical ID: The CS4103’s node address determined during self-identifica-

tion.

6

R

R

Undef

Root: Set when the node becomes root.

7

PS

R

Undef

Cable Power Active: This bit is set when cable power is detected above

7.5V. If cable power drops below 7.5V the PS bit will be cleared and the

Pwr_fail bit set.

Address 01h

0RHB

RW

0

Root Hold-off Bit: When set, the CS4103 will attempt to become root during

the next tree identify process which is subsequent to a bus reset.

1IBR

RW

0

Initiate Bus Reset: When set, a non-arbitrated long bus reset of 167 µs will

be issued by the CS4103. This bit is self clearing.

2:7

Gap_count

RW

3Fh

Gap Count: Arbitration gap times are tuned to minimize bus idle time with

this field. Gap times may be optimized for a specific bus configuration. Two

bus resets return gap_count to 3Fh.

Address 02h

0:2

Extended

R

111

Extended: A value of seven is assigned to this field indicating that the

extended PHY register map has been implemented.

3RSVD

--

--

Reserved

4:7

Total_ports

R

1100

Total Ports: This field shows the number of ports implemented by the

CS4103. The CS4103 utilizes three ports.

Address 03h

0:2

Max_speed

R

010

Maximum Speed: Indicates CS4103 operational speeds. A value of 010

indicates the CS4103 supports 98.304, 196.608, and 393.216Mbit/sec oper-

ation.

3RSVD

--

--

Reserved

4:7

Delay

R

0000

Delay: Worst-case repeater delay equals 144 + (delay * 20) ns.