MAX5116EEE datasheet(4/19 Pages) MAXIM

4 / 19 page

Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial

Interface

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +5.25V, GND = 0, REFH_ = VDD, REFL_ = GND, RLOAD = 5k

Ω, CL = 100pF, TA = -40°C to +85°C, unless otherwise

noted. Typical values are at VDD = +3.0V and TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL TIMING (Figure 4, Note 8)

SCL Clock Frequency

fSCL

400

kHz

Setup Time for START Condition

tSU:STA

0.6

µs

Hold Time for START Condition

tHD:STA

0.6

µs

SCL High Time

tHIGH

0.6

µs

SCL Low Time

tLOW

1.3

µs

Data Setup Time

tSU:DAT

100

Data Hold Time

tHD:DAT

0.9

µs

SDA, SCL Rise Time

300

SDA, SCL Fall Time

300

Setup Time for STOP Condition

tSU:STO

0.6

µs

Bus Free Time Between a STOP

and START Condition

tBUF

1.3

µs

Pulse Width of Spike Suppressed

tSP

Maximum Capacitive Load for

Each Bus Line

(Note 9)

400

Write NV Register Busy Time

(Note 10)

NONVOLATILE MEMORY RELIABILITY

Data Retention

TA= +85°C

Years

TA= +25°C

200,000

Endurance

TA= +85°C

50,000

Stores

Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design.

Note 2: Guaranteed monotonic.

Note 3: Gain error is defined as:

where VF0,Meas is the DAC voltage with input code F0 hex and VF0,Ideal is the ideal DAC voltage with input code F0 hex or

(VREFH - VREFL) x (240 / 256) + VREFL.

Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND +

0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.

Note 5: Output settling time is measured from the 50% point of the rising edge of the last SCL of the data byte to 0.5 LSB of OUT_’s

final value for a code transition from 10 hex to F0 hex.

Note 6: Crosstalk is defined as the coupling from a DAC switching from code 00 hex to code FF hex to any other DAC that is in a

steady state at code 00 hex.

Note 7: Reference feedthrough is defined as the coupling from one driven reference with input code = FF hex to any other DAC

output with the reference of the DAC at a constant value and input code = 00 hex.

Note 8: SCL clock period includes rise and fall times tR and tF. All digital input signals are specified with tR = tF = 2ns and timed

from a voltage level of (VIL + VIH) / 2.

Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to

this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf.

Note 10: The busy time begins from the initiation of the stop pulse.

256

×−

−

()

ZCE

F Meas

F Ideal

REFH

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