CYUSB306X datasheet(8/37 Pages) CYPRESS

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CYUSB306X

Document Number: 001-87516 Rev. *L

Page 8 of 37

The I2C controller supports bus frequencies of 400 kHz, and

1 MHz. When VDDIO1 is 1.8 V, 2.5 V, or 3.3 V, the operating

frequencies supported are 400 kHz and 1 MHz. The I2C

controller supports the clock-stretching feature to enable slower

devices to exercise flow control.

The I2C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VDDIO1.

Note: I2C addresses with the pattern 0x0000111x are used inter-

nally and no slave devices with those addresses should be

connected to the bus.

I2S Interface

CX3 has an I2S port to support external audio codec devices.

CX3 functions as I2S Master as transmitter only. The I2S

interface consists of four signals: clock line (I2S_CLK), serial

data line (I2S_SD), word select line (I2S_WS), and master

system clock (I2S_MCLK). CX3 can generate the system clock

as an output on I2S_MCLK or accept an external system clock

input on I2S_MCLK.

The sampling frequencies supported by the I2S interface are

32 kHz, 44.1 kHz, and 48 kHz.

SPI Interface

CX3 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 24 for details on the

modes) with the Start-Stop clock. This controller is a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

Boot Options

CX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the CX3 boot

options:

■ Boot from USB

■ Boot from I2C

■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),

M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents

Reset

Hard Reset

A hard reset is initiated by asserting the RESET# pin on CX3.

The specific reset sequence and timing requirements are

detailed in Figure 11 on page 26 and Table 14 on page 26. All

I/Os are tristated during a hard reset.

An additional reset pin called MIPI_RESET is provided that

resets the MIPI CSI-2 core. It should be pulled down with a

resistor for normal operation.

Soft Reset

There are two types of Soft Reset:

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset – This reset is identical to Hard Reset.

The firmware must be reloaded following a Whole Device

Reset.

Table 2. CX3 Booting Options

PMODE[2:0][1]

Boot From

F11

USB boot

F1F

I2C, On failure, USB boot is enabled

1FF

I2C only

0F1

SPI, On failure, USB boot is enabled

Note

1. F indicates Floating.

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