CYUSB306X datasheet(10/37 Pages) CYPRESS

10 / 37 page

CYUSB306X

Document Number: 001-87516 Rev. *L

Page 10 of 37

Power

CX3 has the following power supply domains:

■ IO_VDDQ: This is a group of independent supply domains for

digital I/Os.

❐ VDDIO1: GPIO, I

2C, JTAG, XRST, XSHUTDOWN and REF-

CLK

❐ VDDIO2: UART and I

2S (except MCLK)

❐ VDDIO3: I

2S_MCLK and SPI

❐ CVDDQ: CLKIN

❐ VDD_MIPI: MIPI CSI-2 clock and data lanes

■ VDD: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

❐ AVDD: This is the 1.2 V supply for the PLL, crystal oscillator,

and other core analog circuits.

❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2 V supply volt-

ages for the USB 3.0 interface.

■ VUSB: This is the 4 V to 6 V power supply for the USB I/O and

analog circuits. This supply powers the USB transceiver

through CX3’s internal voltage regulator. VUSB is internally

regulated to 3.3 V.

Note: The different power supplies have to be powered on or off

in a specific sequence as illustrated in Figure 4.

Power Modes

CX3 supports the following power modes:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐ Normal operating power consumption does not exceed the

sum of ICC Core max and ICC USB max (see DC

Specifications on page 17 for current consumption

specifications).

❐ The I/O power supplies VDDIO2 and VDDIO3 can be turned off

when the corresponding interface is not in use. VDDIO1 should

never be turned off for normal operation.

■ Low-power modes (see Table 5 on page 11):

❐ Suspend mode with USB 3.0 PHY enabled

❐ Standby mode

❐ Core power-down mode

Figure 4. Power-up Sequence

VUSB

(VBUS)

VDD

(VDD, AVDD,

VDD_MIPI)

VDDIO1

CVDDQ, VDDIO2,

VDDIO3

CLK_IN, REFCLK

RESET#

MIPI_RESET

>= 1 ms

XRST

(Image Sensor RESET)

User programmable

in firmware

<= 10 ms

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