CYUSB306X datasheet(9/37 Pages) CYPRESS

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CYUSB306X

Document Number: 001-87516 Rev. *L

Page 9 of 37

Clocking

CX3 requires two clocks for normal operation:

1. A 19.2-MHz clock to be connected at the CLKIN pin

2. A 6-MHz to 40-MHz clock to be connected at the REFCLK pin

Clock inputs to CX3 must meet the phase noise and jitter require-

ments specified in Table 3 on page 9.

The input clock frequency is independent of the clock and data

rate of the CX3 core or any of the device interfaces (including the

CSI-2 Rx Port). The internal PLL applies the appropriate

clock-multiply option depending on the input frequency.

Note: REFCLK and CLKIN must have either separate clock

inputs or if the same source is used, the clock must be passed

through a buffer with two outputs and then connected to the clock

pins.

32-kHz Watchdog Timer Clock Input

CX3 includes a watchdog timer. The watchdog timer can be used

to interrupt the ARM926EJ-S core, automatically wake up the

CX3 in Standby mode, and reset the ARM926EJ-S core. The

watchdog timer runs a 32-kHz clock, which may be optionally

supplied from an external source on a dedicated CX3 pin.

The firmware can disable the watchdog timer.

Table 4 provides the requirements for the optional 32-kHz clock

input

Table 3. CX3 Input Clock Specifications

Parameter

Description

Specification

Units

Min

Max

Phase noise

100-Hz offset

–

–75

1-kHz offset

–

–104

10-kHz offset

–

–120

100-kHz offset

–

–128

1-MHz offset

–

–130

Maximum frequency deviation

–

150

ppm

Duty cycle

–

Overshoot

–

Undershoot

–

–3

Rise time/fall time

–

Table 4. 32-kHz Clock Input Requirements

Parameter

Min

Max

Units

Duty cycle

Frequency deviation

–

±200

ppm

Rise time/fall time

–

200

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