CYUSB306X datasheet(11/37 Pages) CYPRESS

11 / 37 page

CYUSB306X

Document Number: 001-87516 Rev. *L

Page 11 of 37

Table 5. Entry and Exit Methods for Low-Power Modes

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend Mode with

USB 3.0 PHY

Enabled

■ Power consumption in this mode does not

exceed ISB1

■ USB 3.0 PHY is enabled and is in U3 mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block

alone is operational with its internal clock,

while all other clocks are shut down

■ All I/Os maintain their previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on or off

individually

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ All transactions must be completed before

CX3 enters suspend mode (state of

outstanding transactions are not

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■ Firmware executing on

ARM926EJ-S core can put CX3 into

the suspend mode. For example, on

USB suspend condition, the firmware

may decide to put CX3 into suspend

mode

■ D+ transitioning to low

or high

■ D- transitioning to low

or high

■ Resume condition on

SSRX±

■ Detection of VBUS

■ Level detect on

UART_CTS

(programmable

polarity)

■ Assertion of RESET#

Standby Mode

■ The power consumption in this mode does

not exceed ISB3

■ All configuration register settings and

program/data RAM contents are

preserved. However, data in the buffers or

other parts of the data path, if any, is not

guaranteed. Therefore, the external

processor should take care that the data

needed is read before putting CX3 into the

standby mode

■ The program counter is reset after waking

up from the standby mode

■ GPIO pins maintain their configuration

■ Internal PLL is turned off

■ USB transceiver is turned off

■ ARM926EJ-S core is powered down.

Upon wakeup, the core re-starts and runs

the program stored in the program/data

RAM

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on or off

individually

■ The firmware executing on

ARM926EJ-S core or external

processor configures the appropriate

■ Detection of VBUS

■ Level detect on

UART_CTS

(programmable

polarity)

■ Assertion of RESET#

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