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LTM2889

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APPLICATIONS INFORMATION

Ideal Passive Behavior to CAN Bus With Supply Off

When the power supply is removed or the chip is in shut-

down, the CANH and CANL pins are in a high impedance

state. The receiver inputs are isolated from the CANH and

CANL nodes by FET switches which open in the absence

of power, thereby preventing the resistor dividers on the

receiver input from loading the bus. The high impedance

state of the receiver is limited by ESD clamps inboard of

the 40k input resistors to a typical range of –0.5V to 11V.

Forbusvoltagesoutsidethisrange,thecurrentflowinginto

the receiver is governed by the conduction voltages of the

ESD device and the 40k nominal receiver input resistance.

DeviceNet Compatibility

DeviceNet is a network standard based on the CAN bus.

The DeviceNet standard places requirements on the trans-

ceiver that exceed those of the ISO 11898-2 standard.

The LTM2889 meets the DeviceNet requirements listed

in Table 2.

DeviceNet employs a 5-pin connector with conductors for

Power+, Power–, CANH, CANL, and Drain. The power is

24VDC, and the Drain wire is connected to the cable shield

for shielded cables. The Power– pin may be connected to

LTM2889 GND2, but the Power+ must not be connected

to the LTM2889 VCC2 pin.

Table 2: DeviceNet Requirements

PARAMETER

DeviceNet

REQUIREMENT

ISO 11898-2

REQUIREMENT

LTM2889

Number of Nodes

N/A

166

Minimum Differential

Input Resistance

20k

10k

50k

Differential Input

Capacitance

25pF (Max)

10pF (Nom)

8.4pF (Typ)

(Note 6)

Bus Pin Voltage Range

(Survivable)

–25V to 18V

–3V to 16V

(for 12V Battery)

–60V to 60V

Bus Pin Voltage Range

(Operation)

–5V to 10V

–2V to 7V

–36V to 36V

(VCC = 5V)

Connector Mis-Wiring

Tests, All Pin-Pin

Combinations

±18V

N/A

±60V

(See Below)

The DeviceNet mis-wiring tests involve connecting an

18V supply to each of the 20 possible pin pair/polarity

combinations on the 5-pin connector. The ±60V tolerance

of the LTM2889 with respect to GND2 ensures that the

LTM2889willpassallthemis-wiringtestswithoutdamage.

PCB Layout Considerations

The high integration of the LTM2889 makes PCB layout

very simple. However, to optimize its electrical isolation

characteristics, EMI, and thermal performance, some

layout considerations are necessary.

• Under heavily loaded conditions PVCC and GND current

can exceed 300mA. Sufficient copper must be used

on the PCB to insure resistive losses do not cause the

supply voltage to drop below the minimum allowed

level. Similarly, the VCC2 and GND2 conductors must

be sized to support any external load current. These

heavy copper traces will also help to reduce thermal

stress and improve the thermal conductivity.

• Input and Output decoupling is not required, since

these components are integrated within the package.

An additional bulk capacitor with a value of 6.8μF to

22μF with 1Ω to 3Ω of ESR is recommended. The high

ESR of this capacitor reduces board resonances and

minimizes voltage spikes caused by hot plugging of

the supply voltage. For EMI sensitive applications, an

additional low ESL ceramic capacitor of 1μF to 4.7μF,

placed as close to the power and ground terminals as

possible, is recommended. Alternatively, a number of

smaller value parallel capacitors may be used to reduce

ESL and achieve the same net capacitance.

• Do not place copper on the PCB between the inner col-

umns of pads. This area must remain open to withstand

the rated isolation voltage.

• The use of solid ground planes for GND and GND2

is recommended for non-EMI critical applications to

optimize signal fidelity, thermal performance, and to

minimize RF emissions due to uncoupled PCB trace

conduction. The drawback of using ground planes,

where EMI is of concern, is the creation of a dipole

antennastructurewhichcanradiatedifferentialvoltages

formed between GND and GND2. If ground planes are

used it is recommended to minimize their area, and

use contiguous planes as any openings or splits can

exacerbate RF emissions.

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