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AM3351 Datasheet(PDF) 183 Page - Texas Instruments |
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AM3351 Datasheet(HTML) 183 Page - Texas Instruments |
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183 / 252 page ![]() A1 A2 AM335x Address and Control Output Buffer DDR3 Address and Control Input Buffers AT Vtt Address and Control Terminator Rtt A1 A2 AM335x Differential Clock Output Buffer DDR3 Differential CK Input Buffer Routed as Differential Pair AT Rcp Clock Parallel Terminator A1 A2 AT Rcp Cac VDDS_DDR 0.1 µF + – + – 183 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 www.ti.com SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright © 2011–2016, Texas Instruments Incorporated 7.7.2.3.4.2 One DDR3 Device One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one 16-bit bank. 7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device Figure 7-58 shows the topology of the CK net classes and Figure 7-59 shows the topology for the corresponding ADDR_CTRL net classes. Figure 7-58. CK Topology for One DDR3 Device Figure 7-59. ADDR_CTRL Topology for One DDR3 Device |
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