AM3351 datasheet(186/252 Pages) TI1

186 / 252 page

Rtt

Vtt

(A)

CACLMX

CACLMY

186

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

SPRS717J – OCTOBER 2011 – REVISED APRIL 2016

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Peripheral Information and Timings

7.7.2.3.6 Routing Specification

7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this

skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter

traces up to the length of the longest net in the net class and its associated clock. A metric to establish

this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the

length between the points when connecting them only with horizontal or vertical segments. A reasonable

trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address

Control Longest Manhattan distance.

Given the clock and address pin locations on the AM335x device and the DDR3 memories, the maximum

possible Manhattan distance can be determined given the placement. Figure 7-66 shows this distance for

two loads. The specifications on the lengths of the transmission lines for the address bus are determined

from this distance. CACLM is determined similarly for other address bus configurations; that is, it is based

on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these

specifications are contained in Table 7-66.

It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the

DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net

class that satisfies this criteria and use as the baseline for CK and ADDR_CTRL skew matching and length control.

The length of shorter CK and ADDR_CTRL stubs as well as the length of the terminator stub are not included in this

length calculation. Nonincluded lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 7-66. CACLM for Two Address Loads on One Side of PCB

Table 7-66. CK and ADDR_CTRL Routing Specification(1)(2)(3)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

A1 + A2 length

2500

mils

A1 + A2 skew

mils

A3 length

660

mils

A3 skew(4)

mils

A3 skew(5)

125

mils

AS length

100

mils

AM3351 Datasheet(PDF) 186 Page - Texas Instruments

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