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AM3351 Datasheet(PDF) 189 Page - Texas Instruments |
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AM3351 Datasheet(HTML) 189 Page - Texas Instruments |
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189 / 252 page  189 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 www.ti.com SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright © 2011–2016, Texas Instruments Incorporated 7.8 I 2C For more information, see the Inter-Integrated Circuit (I2C) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual. 7.8.1 I 2C Electrical Data and Timing Table 7-68. I2C Timing Conditions – Slave Mode PARAMETER STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX Output Condition Cb Capacitive load for each bus line 400 400 pF Table 7-69. Timing Requirements for I2C Input Timings (see Figure 7-68) NO. STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 µs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs 3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 µs 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(1) ns 7 th(SCLL-SDAV) Hold time, SDA valid after SCL low 0(2) 3.45(3) 0(2) 0.9(3) µs 8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 9 tr(SDA) Rise time, SDA 1000 300 ns 10 tr(SCL) Rise time, SCL 1000 300 ns 11 tf(SDA) Fall time, SDA 300 300 ns 12 tf(SCL) Fall time, SCL 300 300 ns 13 tsu(SCLH-SDAH) Setup time, high before SDA high (for STOP condition) 4 0.6 µs 14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 0 50 ns (1) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-Bus Specification) before the SCL line is released. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. |
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