MP2661 datasheet(4/35 Pages) MPS

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MP2661 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL AND POWER PATH

MP2661 Rev. 1.03

www.MonolithicPower.com

4/9/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

PACKAGE REFERENCE

TOP VIEW

WCSP-9 (1.55mmx1.55mm)

PIN FUNCTIONS

Package

Pin #

Name

I/O

Description

Power

Input power. Place a ceramic capacitor (≥1μF) from IN to GND as close to the

IC as possible.

SYS

Power

System power supply. Place a ceramic capacitor (≥2.2μF) from SYS to GND as

close to the IC as possible.

BATT

Power

Battery. Place a ceramic capacitor (≥2.2μF) from BATT to GND as close to the

IC as possible.

NTC

Temperature sense input. Connect a negative temperature coefficient

thermistor to NTC. Program the hot and cold temperature window with a resistor

divider from VDD to NTC to GND. The charge is suspended when NTC is out of

range.

INT

Open drain interrupt output. INT can send the charging status and fault

interruption to the host. INT is also used to disconnect the system from the

battery. Pull INT from high to low for >16s.The battery MOSFET is off and turns

on automatically after >4s, regardless of the INT state. the external pull up

resistor at INT should be not smaller than 100kΩ.

VDD

Internal control power supply. Connect a ceramic capacitor(0.1μF)from VDD to

GND. No external load is allowed.

SDA

I/O

2C interface data. Connect SDA to the logic rail through a 10kΩ resistor.

SCL

I/O

2C interface clock. Connect SCL to the logic rail through a 10kΩ resistor.

GND

Power Ground.

MP2661 Datasheet(PDF) 4 Page - Monolithic Power Systems

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