LMX2572LP datasheet(14/82 Pages) TI1

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VCO

RFoutA

÷2,4,8,16,

32,64,128,

256

RFoutB

LMX2572LP

SNAS764 – MAY 2018

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7.3.4 PLL N Divider and Fractional Circuitry

The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to

(232 – 1). The integer portion of N (PLL_N) is the whole part of the N divider value, and the fractional portion,

Nfrac = PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM and PLL_DEN are software

programmable. The higher the denominator, the finer the resolution step of the output. For example, even when

using fPD = 200 MHz, the output can increment in steps of 200 MHz / (2

32 – 1) = 0.0466 Hz. Equation 2 shows

the relationship between the phase detector and VCO frequencies. Note that in SYNC mode, there is an extra

divider that is not shown in Equation 2.

fVCO = fPD × [PLL_N + (PLL_NUM / PLL_DEN)]

(2)

The multi-stage noise-shaping (MASH) sigma-delta modulator that controls the fractional division is also

programmable from integer mode to fourth order. All of these settings work for integer channel where PLL_NUM

= 0. To make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

The N divider has minimum value restrictions based on the modulator order. Furthermore, the PFD_DLY_SEL bit

must be programmed in accordance to Table 3.

Table 3. Minimum N Divider Restrictions

VCO

FREQUENCY

(GHz)

MASH ORDER

INTEGER

FIRST ORDER

SECOND ORDER

THIRD ORDER

FOURTH ORDER

PFD_DLY_SEL

fVCO < 4

≤ fVCO < 4.9

4.9

≤ fVCO ≤ 6.4

7.3.5 Voltage-Controlled Oscillator

The LMX2572LP includes a fully integrated VCO. The VCO generates a frequency which varies with the tuning

voltage from the loop filter. The entire VCO frequency range, 3.2 to 6.4 GHz, covers an octave that allows the

channel divider to take care of frequencies below the lower bound.

To reduce the VCO tuning gain, thus improving the VCO phase noise performance, the VCO frequency range is

divided into 6 different frequency bands. This creates the need for frequency calibration to determine the correct

frequency band given in a desired output frequency. The VCO is also calibrated for amplitude to optimize phase

noise. These calibration routines are activated any time that the R0 register is programmed with the FCAL_EN bit

equals one. It is important that a valid OSCin signal must present before VCO calibration begins. This device will

support a full sweep of the valid temperature range of 125°C (–40°C to 85°C) without having to re-calibrate the

VCO. This is important for continuous operation of the synthesizer under the most extreme temperature variation.

7.3.6 Channel Divider

To go below the VCO lower bound of 3.2 GHz, the channel divider can be used. The channel divider consists of

several segments, and the total division value is equal to the multiplication of them. Therefore, not all values are

valid.

Figure 22. Channel Divider

7.3.7 Output Buffer

The output buffers are differential push-pull type buffers, thus no external pullup to VCC is required. The output

impedance of the buffer is very small, and as such, the buffer can be AC-coupled to drive a 50-Ω load. Output

power of the buffer can be programed to various levels. The buffer can be disabled while still keeping the PLL in

lock.

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