ZL2004 datasheet(32/42 Pages) RENESAS

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ZL2004

FN6846 Rev. 3.00

Page 32 of 42

February 15, 2011

Table 20. Tracking Mode Configuration

RSS

UVLO

Tracking

Ratio

Upper Track Limit

Ramp-up / Ramp-down Behavior

19.6 k

4.5 V

100%

Limited by target

voltage

Output not allowed to decrease before PG

21.5 k

Output will always follow VTRK

23.7 k

Limited by VTRK

pin voltage

Output not allowed to decrease before PG

26.1 k

Output will always follow VTRK

28.7 k

50%

Limited by target

voltage

Output not allowed to decrease before PG

31.6 k

Output will always follow VTRK

34.8 k

Limited by VTRK

pin voltage

Output not allowed to decrease before PG

38.3 k

Output will always follow VTRK

42.2 k

10.8 V

100%

Limited by target

voltage

Output not allowed to decrease before PG

46.4 k

Output will always follow VTRK

51.1 k

Limited by VTRK

pin voltage

Output not allowed to decrease before PG

56.2 k

Output will always follow VTRK

61.9 k

50%

Limited by target

voltage

Output not allowed to decrease before PG

68.1 k

Output will always follow VTRK

75 k

Limited by VTRK

pin voltage

Output not allowed to decrease before PG

82.5 k

Output will always follow VTRK

6.9 I2C/SMBus Communications

The ZL2004 provides an I

2C/SMBus digital interface

that enables the user to configure all aspects of the

device operation as well as monitor the input and

output parameters. The ZL2004 can be used with any

standard 2-wire I

2C host device. In addition, the device

is compatible with SMBus version 2.0 and includes an

SALRT line to help mitigate bandwidth limitations

related to continuous fault monitoring. Pull-up resistors

are required on the I

2C/SMBus. The ZL2004 accepts

most standard PMBus commands. When controlling

the device with PMBus commands, it is recommended

that the enable pin is tied to SGND.

6.10 I2C/SMBus Device Address Selection

When communicating with multiple SMBus devices

using the I

2C/SMBus interface, each device must have

its own unique address so the host can distinguish

between the devices. The device address can be set

according to the pin-strap options listed in Table 21.

Address values are right-justified.

Table 21. SMBus Device Address Selection

SA0

LOW

OPEN

HIGH

SA1

LOW

0x20

0x21

0x22

OPEN

0x23

0x24

0x25

HIGH

0x26

0x27

Reserved

If additional device addresses are required, a resistor

can be connected to the SA0 pin according to Table 22

to provide up to 25 unique device addresses. In this

case, the SA1 pin should be tied to SGND.

If more than 25 unique device addresses are required or

if other SMBus address values are desired, both the SA0

and SA1 pins can be configured with a resistor to SGND

according to the following equation and Table 23.

SMBus address = 25 x (SA1 index) + (SA0 index)

(in decimal)

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