ZL2004 datasheet(17/42 Pages) RENESAS

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ZL2004

FN6846 Rev. 3.00

Page 17 of 42

February 15, 2011

5.6 Switching Frequency and PLL

The ZL2004 incorporates an internal phase-locked

loop (PLL) to clock the internal circuitry. The PLL can

be driven by an external clock source connected to the

SYNC pin. When using the internal oscillator, the

SYNC pin can be configured as a clock source for

other Zilker Labs devices.

The SYNC pin is a unique pin that can perform

multiple functions depending on how it is configured.

The CFG pin is used to select the operating mode of

the SYNC pin as shown in Table 12. Figure 13

illustrates the typical connections for each mode.

Table 12. SYNC Pin Function Selection

CFG Pin

SYNC Pin Function

LOW

SYNC is configured as an input

OPEN

Auto Detect mode

HIGH

SYNC is configured as an output

fSW = 400 kHz

Configuration A: SYNC OUTPUT

When the SYNC pin is configured as an output (CFG

pin is tied HIGH), the device will run from its internal

oscillator and will drive the resulting internal oscillator

signal (preset to 400 kHz) onto the SYNC pin so other

devices can be synchronized to it. The SYNC pin will

not be checked for an incoming clock signal while in

this mode.

Configuration B: SYNC INPUT

When the SYNC pin is configured as an input (CFG

pin is tied LOW), the device will automatically check

for a clock signal on the SYNC pin each time EN is

asserted.

The

ZL2004’s

oscillator

will

then

synchronize with the rising edge of the external clock.

The incoming clock signal must be in the range of 200

kHz to 1.4 MHz and must be stable when the enable

pin is asserted. The clock signal must also exhibit the

necessary performance requirements (see Table 3). In

the event of a loss of the external clock signal, the

output voltage may show transient over/undershoot.

If this happens, the ZL2004 will automatically switch

to its internal oscillator and switch at a frequency close

to the previous incoming frequency.

Configuration C: SYNC AUTO DETECT

When the SYNC pin is configured in auto detect mode

(CFG pin is left OPEN), the device will automatically

check for a clock signal on the SYNC pin after enable

is asserted.

If a clock signal is present, The ZL2004’s oscillator

will then synchronize the rising edge of the external

clock. Refer to SYNC INPUT description.

If no incoming clock signal is present, the ZL2004 will

configure the switching frequency according to the

state of the SYNC pin as listed in Table 13. In this

mode, the ZL2004 will only read the SYNC pin

connection during the start-up sequence. Changes to

SYNC pin connections will not affect fSW until the

power (VDD) is cycled off and on.

Table 13. Switching Frequency Selection

SYNC Pin

Frequency

LOW

200 kHz

OPEN

400 kHz

HIGH

1 MHz

Resistor

See Table 14

If the user wishes to run the ZL2004 at a frequency not

listed in Table 13, the switching frequency can be set

using an external resistor, RSYNC, connected between

SYNC and SGND using Table 14.

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