ZL2004 datasheet(33/42 Pages) RENESAS

33 / 42 page

ZL2004

FN6846 Rev. 3.00

Page 33 of 42

February 15, 2011

Table 22. SMBus Address Values

RSA

SMBus

Address

RSA

SMBus

Address

10 k

0x00

34.8 k

0x0D

11 k

0x01

38.3 k

0x0E

12.1 k

0x02

42.2 k

0x0F

13.3 k

0x03

46.4 k

0x10

14.7 k

0x04

51.1 k

0x11

16.2 k

0x05

56.2 k

0x12

17.8 k

0x06

61.9 k

0x13

19.6 k

0x07

68.1 k

0x14

21.5 k

0x08

75 k

0x15

23.7 k

0x09

82.5 k

0x16

26.1 k

0x0A

90.9 k

0x17

28.7 k

0x0B

100 k

0x18

31.6 k

0x0C

Using this method, the user can theoretically configure

up to 625 unique SMBus addresses, however the

SMBus is inherently limited to 128 devices so

attempting to configure an address higher than 128

(0x80) will cause the device address to repeat (i.e,

attempting to configure a device address of 129 (0x81)

would result in a device address of 1. Therefore, the

user should use index values 0-4 on the SA1 pin and

the full range of index values on the SA0 pin, which

will provide 125 device address combinations.

Table 23. SMBus Address Index Values

RSA

SA0 or

SA1

Index

RSA

SA0 or

SA1 Index

10 k

34.8 k

11 k

38.3 k

12.1 k

42.2 k

13.3 k

46.4 k

14.7 k

51.1 k

16.2 k

56.2 k

17.8 k

61.9 k

19.6 k

68.1 k

21.5 k

75 k

23.7 k

82.5 k

26.1 k

90.9 k

28.7 k

100 k

31.6 k

6.11 Digital-DC Bus

The Digital-DC Communications (DDC) bus is used to

communicate between Zilker Labs Digital-DC devices.

This dedicated bus provides the communication

channel

between

devices

for

features

such

sequencing, fault spreading, and current sharing. The

DDC pin on all Digital-DC devices in an application

should be connected together. A pull-up resistor is

required on the DDC bus in order to guarantee the rise

time as follows:

Rise time = RPU * CLOAD ≈ 1 µs,

where RPU is the DDC bus pull-up resistance and

CLOAD is the bus loading. The pull-up resistor may be

tied to VR or to an external 3.3V or 5V supply as long

as this voltage is present prior to or during device

power-up. As rules of thumb, each device connected to

the DDC bus presents approx 10 pF of capacitive

loading, and each inch of FR4 PCB trace introduces

approx 2 pF. The ideal design will use a central pull-up

resistor that is well-matched to the total load

capacitance. In power module applications, the user

should consider whether to place the pull-up resistor on

the module or on the PCB of the end application. The

minimum pull-up resistance should be limited to a

value that enables any device to assert the bus to a

voltage that will ensure a logic 0 (typically 0.8 V at the

device monitoring point) given the pull-up voltage (5

V if tied to VR) and the pull-down current capability of

the ZL2004 (nominally 4 mA).

6.12 Phase Spreading

When multiple point of load converters share a

common DC input supply, it is desirable to adjust the

clock phase offset of each device such that not all

devices start to switch simultaneously. Setting each

converter to start its switching cycle at a different point

in time can dramatically reduce input capacitance

requirements and efficiency losses. Since the peak

current drawn from the input supply is effectively

spread out over a period of time, the peak current

drawn at any given moment is reduced and the power

losses

proportional

the

IRMS

are

reduced

dramatically.

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