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ZL2004 Datasheet(PDF) 4 Page - Renesas Technology Corp |
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ZL2004 Datasheet(HTML) 4 Page - Renesas Technology Corp |
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4 / 42 page ![]() ZL2004 FN6846 Rev. 3.00 Page 4 of 42 February 15, 2011 Table 3. Electrical Specifications VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C. Boldface limits apply over the operating temperature range, -40°C to +85°C. Parameter Conditions Min 10 Typ Max 10 Unit Input and Supply Characteristics IDD supply current at fSW = 200 kHz IDD supply current at fSW = 1.4 MHz GH no load, GL no load, MISC_CONFIG[7] = 1 – – 16 25 30 50 mA mA IDDS shutdown current EN = 0 V, No I2C/SMBus activity – 6.5 8 mA VR reference output voltage VDD > 6 V, IVR < 50 mA 4.5 5.2 5.7 V V25 reference output voltage VR > 3 V, IV25 < 50 mA 2.25 2.5 2.75 V Output Characteristics Output voltage adjustment range1 VIN > VOUT 0.6 – 3.6 V Output voltage set-point resolution Set using resistors – 10 – mV Set using I2C/SMBus – ±0.025 – % FS2 Output voltage accuracy 3 Includes line, load, temp - 1 – 1 % VSEN input bias current VSEN = 4 V – 80 150 µA Current sense differential input voltage (VOUT referenced) VISENA - VISENB - 50 – 50 mV Current sense input bias current (VOUT referenced, VOUT <= 3.6V) ISENA - 1 – 1 µA ISENB - 100 – 100 µA Soft start delay duration range Set using SS pin or resistor 2 – 20 ms Set using I2C/SMBus 0.002 – 500 s Soft start delay duration accuracy Turn-on delay (precise mode) 4,5 Turn-on delay (normal mode) 6 Turn-off delay 6 – – – ±0.25 -0.25/+4 -0.25/+4 – – – ms ms ms Soft start ramp duration range Set using SS pin or resistor 2 – 20 ms Set using I2C 0 – 200 ms Soft start ramp duration accuracy – 100 – µs Logic Input/Output Characteristics Logic input bias current EN,PG,SCL,SDA,SALRT pins - 10 – 10 µA MGN input bias current - 1 – 1 mA Logic input low, VIL – – 0.8 V Logic input OPEN (N/C) Multi-mode logic pins – 1.4 – V Logic input high, VIH 2.0 – – V Logic output low, VOL IOL ≤ 4 mA – – 0.4 V Logic output high, VOH IOH ≥ -2 mA 2.25 – – V Notes: 1. Set point adjustment range does not include margin limits. 2. Percentage of Full Scale (FS) with temperature compensation applied. 3. VOUT set-point measured at the termination of the VSEN+ and VSEN- sense points. 4. The device requires approximately 2 ms following an enable signal and prior to ramping its output. The delay accuracy will vary by ±0.25 ms around the 2 ms minimum delay value. 5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable. 6. The devices may require up to a 4 ms delay following an assertion of the enable signal (normal mode) or following the de-assertion of the enable signal. |
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