FT28C010 datasheet(4/30 Pages) FORCE

4 / 30 page

DEVICE OPERATION

Read

Read operations are initiated by both OE and CE LOW.

The read operation is terminated by either CE or OE

returning HIGH. This two line control architecture elimi-

nates bus contention in a system environment. The data

bus will be in a high impedance state when either OE or

is HIGH.

Write

Write operations are initiated when both CE andWE are

LOW and OE is HIGH. The FT28C010 supports both a

and WE controlled write cycle. That is, the address

is latched by the falling edge of eitherCE or WE, which-

ever occurs last. Similarly, the data is latched internally by

the rising edge of either CE or WE, whichever occurs first.

A byte write operation, once initiated, will automatically

continue to completion, typically within 5ms.

Page Write Operation

The page write feature of the FT28C010 allows the entire

memory to be written in 5 seconds. Page write allows

two to two hundred fifty-six bytes of data to be consecu-

tively written to the FT28C010 prior to the commence-

ment of the internal programming cycle. The host can

fetch data from another device within the system during

a page write operation (change the source address), but

the page address (A8 through A16) for each subsequent

valid write cycle to the part during this operation must be

the same as the initial page address.

The page write mode can be initiated during any write

operation. Following the initial byte write cycle, the host

can write an additional one to two hundred fifty six bytes

in the same manner as the first byte was written. Each

successive byte load cycle, started by the WE HIGH to

LOW transition, must begin within 100 µs of the falling

edge of the preceding WE. If a subsequent WE HIGH to

LOW transition is not detected within 100 µs, the internal

automatic programming cycle will commence. There is

no page write window limitation. Effectively the page

write window is infinitely wide, so long as the host

continues to access the device within the byte load cycle

time of 100µs.

Write Operation Status Bits

The FT28C010 provides the user two write operation

status bits. These can be used to optimise a system

write cycle time. The status bits are mapped onto the

I/O bus as shown in Figure 1.

DATA

Polling (I/O7)

The FT28C010 features DATA Polling as a method to

indicate to the host system that the byte write or page

write cycle has completed. DATA Polling allows a simple

bit test operation to determine the status of the FT28C010,

eliminating additional interrupt inputs or external hard-

ware. During the internal programming cycle, any at-

tempt to read the last byte written will produce the

complement of that data on I/O7 (i.e., write data = 0xxx

xxxx, read data = 1xxx xxxx). Once the programming

cycle is complete, I/O7 will reflect true data. Note: If the

FT28C010 is in the protected state and an illegal write

operation is attempted DATA Polling will not operate.

Toggle Bit (I/O6)

The FT28C010 also provides another method for deter-

mining when the internal write cycle is complete. During

the internal programming cycle, I/O 6 will toggle from

HIGH to LOW and LOW to HIGH on subsequent at-

tempts to read the device. When the internal cycle is

complete the toggling will cease and the device will be

accessible for additional read or write operations.

Figure 1. Status Bit Assignment

5TB

43210

I/O

RESERVED

TOGGLE BIT

DATA POLLING

FT28C010-xxxxx-X

Rev 1.1

4/30

2011

FT28C010 Datasheet(PDF) 4 Page - Force Technologies Ltd

FT28C010 Datasheet(HTML) 4 Page - Force Technologies Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL