11

ATSAM9753

1774D–DRMSD–11/02

Timing Diagrams

All timings are relative to 11.2896 MHz crystal between X1 and X2.

Figure 3. Scanning Timings (Keyboard, Switches, LEDs and Sliders) Timing Diagram

Table 6. Scanning Timing Parameters

Symbol

Parameter

Min

Typ

Max

Unit

t

KBD

Keyboard access (KBDIO high time)

1.4

µs

Switches/leds access (KBDIO low time)

4.3

µs

t

SCLK

Internal scanning clock period

354

ns

t

KA

Break (contact1) and Make (contact2) data from keyboard valid

from rising KBDIO

1.2

µs

t

KD

Break (contact1) and Make (contact2) data from Keyboard

floating from rising KBDIO

1.3

1.6

µs

Switch data valid from falling KBDIO

4µs

t

IOD

Switch data floating from falling KBDIO

4.1

4.4

µs

t

IOG

LED data MK guard time

177

27

ns

LED data floating from rising KBDIO

088

ns

t

VA

Analog V

and hold voltage follow mode)

1µs

t

VD

Analog V

mode)

2.2

µs

SCLK

KBDIO

ROW[2:0]

BR[10:0]

MK[10:0]

VIN