T48C893 datasheet(12/82 Pages) ATMEL

12 / 82 page

T48C893

Rev. A4, 22-Jan-02

12 (82)

INT5 active

INT7 active

INT2 pending

SWI0

INT2 active

INT0 pending

INT0 active

INT2

RTI

INT5

INT3 active

INT3

RTI

INT7

Time

Main /

Autosleep

Main /

Autosleep

94 8978

Figure 8. Interrupt handling

Interrupt Processing

For processing the eight interrupt levels, the MARC4

includes an interrupt controller with two 8-bit wide

”interrupt pending” and ”interrupt active” registers. The

interrupt controller samples all interrupt requests during

every non-I/O instruction cycle and latches these in the

interrupt pending register. If no higher priority interrupt

is present in the interrupt active register, it signals the

CPU to interrupt the current program execution. If the

interrupt enable bit is set, the processor enters an interrupt

acknowledge cycle. During this cycle a short call

(SCALL) instruction to the service routine is executed

and the current PC is saved on the return stack. An

interrupt service routine is completed with the RTI

instruction. This instruction sets the interrupt enable flag,

resets

the

corresponding

bits

the

interrupt

pending/active register and fetches the return address

from the return stack to the program counter. When the

interrupt enable flag is reset (triggering of interrupt

routines are disabled), the execution of new interrupt

service routines is inhibited but not the logging of the

interrupt requests in the interrupt pending register. The

execution of the interrupt is delayed until the interrupt

enable flag is set again. Note that interrupts are only lost

if an interrupt request occurs while the corresponding bit

in the pending register is still set (i.e., the interrupt service

routine is not yet finished).

It should also be noted that automatic stacking of the RBR

is not carried out by the hardware and so if ROM banking

is used, the RBR must be stacked on the expression stack

by the application program and restored before the RTI.

After a master reset (power-on, brown-out or watchdog

reset), the interrupt enable flag and the interrupt pending

and interrupt active register are all reset.

Interrupt Latency

The interrupt latency is the time from the occurrence of

the interrupt to the interrupt service routine being

activated. In MARC4 this is extremely short (taking

between 3 to 5 machine cycles depending on the state of

the core).

T48C893 Datasheet(PDF) 12 Page - ATMEL Corporation

T48C893 Datasheet(HTML) 12 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL